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This article reviews the recent developments and challenges in spintronic based spiking neural networks (SNNs). The present CPUs and GPUs are powerful tools that are capable of computing complex artificial intelligence (AI) tasks, yet they face several challenges. The systems utilizing machine learning techniques require extensive computations including vector-matrix multiplication. The traditional von Neumann architecture is inefficient in the hardware implementation of such systems. Neuromorphic architectures are computationally more efficient that ushers the era of high-performance hardware for AI applications. This also caters to the need of hardware solutions for biologically inspired in-memory computing functionality using nonvolatile memory (NVM). These biologically inspired networks have attracted a great attention due to their inherent computational efficiency in performing pattern/speech recognition and image classification tasks. During the last decade, SNNs have emerged as one of the suitable solutions for imitating the biological brain. Information is temporarily encoded in SNNs and the spikes serve as a mode of communication between the neurons. Various NVM devices such as spin-based memories, resistive randomaccess memory (RRAM), phase change memory (PCM), and conductive-bridging RAM (CBRAM) have been explored for the hardware implementation of NNs. Spin-based memory devices demonstrate much more energy efficiency while providing superior information processing capabilities than other NVMs. These devices also provide high endurance, scalability, CMOS compatibility, and ultralow power consumption characteristics. The spiking functionality in neurons can be easily mapped to various spin devices with synaptic learning, therefore, paving the path for future AI hardware solutions. [ABSTRACT FROM AUTHOR]

This article presents a multilevel design for spin–orbit torque (SOT)-assisted spin-transfer torque (STT)-based 4-bit magnetic random access memory (MRAM). Multilevel cell (MLC) design is an effective solution to increase the storage capacity of MRAM. The conventional SOT-MRAMs enable an energy-efficient, fast, and reliable write operation. However, unlike STT-MRAM, these cells take more area and require two access transistors per cell. This poses significant challenges in the use of SOT-MRAMs for high-density memory applications. To address these issues, we propose an MLC that can store 4 bits and requires only three access transistors. The effective area per bit of the proposed cell is nearly 58% lower than that of the conventional 1-bit SOT-MRAM cell. The combined effect of SOT and STT has been incorporated to design SOT-STT-based MLC that enables more energy-efficient and faster write operation than the regular MLCs. The results show that SOT–STT-based 4-bit MLC is 52.9% and 40% more efficient in terms of latency and energy consumption, respectively, when compared to 3-bit SOT-/STT-based MLC. [ABSTRACT FROM AUTHOR]

Computing-in-memory (CiM) architectures have experienced faster growth with the emergence of nanoscale magnetic tunnel junction (MTJ) spintronic devices due to their nonvolatile and CMOS compatible architectures. Recently, spin-transfer torque (STT) and spin Hall effect (SHE)-based several CiM designs have been published. The majority of these designs employ a single-level cell (SLC) memory array and require high write energy to perform logic computations. To mitigate these problems, we propose novel SLC and multilevel cell (MLC) differential spin Hall (DSH) magnetic random access memory (MRAM)-based CiM designs that employed MTJs with field-free switching technique using the in-plane magnetic (IPM) layer. Initially, SLC DSH-MRAM-based magnetic full adder (MFA) is proposed. Furthermore, DSH-MRAM series MLC (sMLC)-based CiM implementations of AND/OR/XOR gates and 1 bit MFA are presented in this work. This DSH-sMLC-based CiM structure exploits a reconfigurable precharge sense amplifier (RPCSA) and innovative MTJ reference mechanism to perform each of the logic operations within a single evaluation cycle and provides complementary logic outputs useful for further computations. The comparative performance analysis of the proposed CiM MFA with SHE-based and voltage-controlled SHE-sMLC-based CiM designs reveals 52% and 33% improvement in write energy, respectively. The proposed design saves 34% area compared to the SHE-based counterpart. [ABSTRACT FROM AUTHOR]

Spin-torque-based magnetic random access memories (MRAMs) have emerged as a promising option for next-generation data-centric computing systems. Multi-level cell (MLC) configuration is an efficient method to increase storage density. In this article, we propose a series triple-level cell (sTLC) architecture based on spin-transfer torque (STT) and spin–orbit torque (SOT) switching mechanisms. The proposed hybrid STT/SOT sTLC MRAM architecture is capable of storing 3 bits of data using a maximum of two writing steps. However, most of the switching transitions (72%) use only single-step writing. The simulation results of the sTLC MRAM showed 82% and 68% saving in the write energy compared with previously published STT and STT-/SOT-based TLC structures, respectively. One-step parallel read operation for sTLC is presented in this work that enables ultra-fast reading of 3 bits of data. Furthermore, a novel sTLC-based computing-in memory (CiM) architecture is proposed, and high-performance AND/OR/XOR and magnetic full-adder (MFA) logic circuits have been implemented. The proposed sTLC-based CiM MFA shows 33% lesser transistor counts with nearly equivalent energy performance in comparison to the recently published spin-Hall effect (SHE)-based CiM MFA. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) has emerged as a viable candidate for next-generation memory and logic applications. Manipulation of the magnetic and electric field can control the spin and charge state variables that are of utmost importance in spintronics devices. In this article, the modeling of voltage-controlled spin–orbit torque (VCSOT)-based magnetic random access memory (MRAM) is demonstrated. VCSOT MRAM is an ultrafast device owing to a magnetic switching time of 0.7 ns. It is more energy-efficient as compared to spin–orbit torque (SOT) MRAM. VCSOT MRAM has been exemplified for multilevel cell (MLC) application to enhance the memory integration density. Two-bit serial MLC (sMLC) and parallel MLC (pMLC) designs are proposed using VCSOT MRAM. These MLCs are more energy-efficient as compared to SOT-MLCs. Moreover, 2-bit sMLC and pMLC VCSOT-MRAM significantly reduce average write energy by 91.5% and 49.6%, respectively, as compared to SOT-based MLC. Performance metrics for these devices have been illustrated, which shows the negligible read disturbance and write error rates. [ABSTRACT FROM AUTHOR]

The compressors are widely used as bit compressing cells having key applications with multi-operand addition and multiplication hardware. As the CMOS technology scales down below 45 nm technology nodes, static power dissipation becomes a major concern. To overcome this constraint, spin transfer torque magnetic random access memory (STT-MRAM)-based hybrid CMOS/MTJ architectures are being used. Inception of perpendicular magnetic tunnel junction (PMTJ) has enhanced the growth of spintronics-based hybrid architectures, due to their low switching current, scalability, non-volatility, and CMOS compatibility. Recently, a large number of circuits based on STT-MRAM have been proposed. However, they have limitations related to reliability and high write energy. In this article, we propose a differential spin Hall MRAM (DSH-MRAM)-based hybrid CMOS/MTJ magnetic 4-2 compressor. A write voltage of 0.4 V and 300 ps current pulse are used to switch the magnetization state of the MTJs. When compared with previous STT-MRAM-based designs, the proposed compressor shows 97% improvement in power-delay product (PDP) characteristics. The write circuit in DSH-MRAM consumes merely 5 nW in comparison to $2~\mu \text{W}$ by conventional STT-MRAM designs. Moreover, the narrow write pulse promotes the proposed design for input frequencies up to 1 GHz. [ABSTRACT FROM AUTHOR]

Image dehazing is an essential preprocessing stage for several applications such as surveillance, long-range imaging, automatic driver-assistance system (ADAS), and remote sensing. Haze particles degrade visible-band images more severely than the infrared images due to scattering phenomena. Therefore, infrared data can be effectively utilized to enhance the visibility of color images captured in a hazy environment. In this brief, for the first time, a multispectral transmission map fusion approach is presented, wherein a haze-aware weight generation scheme is used to improve transmission map in specific regions. This achieves significant quantitative improvement as compared with the existing methods. In addition, the method is extremely suitable for hardware implementation. Therefore, a low-cost very large-scale integration (VLSI) architecture is also presented. The application-specified integrated circuit (ASIC) and field-programmable gate array (FPGA) implementations dissipate 3.45- and 57-mW power at 150 MHz, respectively. Both ASIC and FPGA achieve a high throughput of 450 and 308 Mpixels/s, respectively. The design does not require any external memory such as dynamic random access memory, thus making it suitable for on-chip processing that can be closely integrated with an image sensor. [ABSTRACT FROM AUTHOR]

Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimize the single-level cell and multilevel cell (MLC) STT-MRAMs in terms of area, energy, and read–write operations at ultralow power supply voltages. In this paper, a parallel MLC (pMLC) STT-MRAM (20–50 nm) is proposed to provide smaller footprint area, energy efficient, and optimized read–write operations with very low failure probabilities at the supply voltage of 1 V. These designs utilize high- k gate dielectric gate-all-around silicon nanowire-based vertical NMOS transistor as a switching device. The PMTJ device is modeled using Verilog-A. The HSPICE simulation results affirm the suitability of pMLC designs, e.g., 3-bit pMLC design exhibits, switching error probability much less than 10−9, and average write energy of <2 pJ with minimum cell-area at the pulsewidth of 10 ns. [ABSTRACT FROM PUBLISHER]

Conventional spin transfer torque (STT) magneto-resistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric- $k$ ) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different- $k$ sidewall spacers, i.e., one side high- $k$ and other side low- $k$ spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%. [ABSTRACT FROM PUBLISHER]

In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs generally lowers the data-retention capability. Hence, a different approach to reduce power dissipation using a novel select device should be considered. This paper, therefore, explores the STT MRAM with vertical silicon nanowire gate all around (GAA) high- $k$ select device for superior performance. The MTJ is stacked above the vertical GAA device, so that both occupy the same footprint area to achieve high array density. Furthermore, enhancement of current drive using high- k$ gate dielectric and its impact on the STT MRAMs are analyzed at different feature sizes. The proposed STT MRAM cell with high- k$ dielectric (HfO2) lowers the power dissipation by 8%–25% and increases the write margins (WMs) up to 38%, with negligible increment in delay in comparison with the GAA device using low- k . The proposed asymmetric high- $k$ cell offers a substantially larger tradeoff window between high WMs and low power dissipation. [ABSTRACT FROM AUTHOR]

The incredible potentials of spin transfer torque (STT) magnetic random access memories (MRAMs) give them an edge over other memory technologies. Most of the projections show them as universal memory in the future; however, their evolution is still in a rudimentary stage. Attaining a high density in STT MRAMs is imperative to keep pace with the scaling scenario in field effect transistors (FETs) and hence competitive with future processors. A vertical or a two terminal select device can be a possible solution to achieve the high-density problem. A suitable platform is required for simulating a hybrid magnetic tunnel junction (MTJ)/FET circuit before an actual fabrication is done. However, most simulation tools do not have the capability to model hybrid MTJ/FET devices. Also, the SPICE compatible models for such devices and other novel structures like vertical FET are not available. This paper addresses the above-mentioned concerns and proposes a model for MTJ (coded in C++) and a simulation platform for hybrid MTJ/FET device-circuit co-design with physics-based models. The proposed model is validated using mixed mode simulations. [ABSTRACT FROM AUTHOR]

Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual-k spacers technology to enhance the electrostatic integrity of underlap FinFETs. For the first time, we investigate the circuit performance such as that of static RAMs (SRAMs), based on the proposed dual-k spacer FinFETs. The proposed structure enhances SRAMs performance in terms of robustness, access times, and the leakage power during all possible modes of operation. The hold, read, and write-margin increases by 8.7%, 9.4%, and 10.4%, respectively, as compared with conventional FinFET SRAM. Furthermore, the read and write access times reduces by 56% and 17.1%, respectively. Moreover, the standby leakage power is also reduced by \sim73\% compared with the conventional FinFET-based SRAM while occupying same bit-cell area. [ABSTRACT FROM PUBLISHER]

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual-k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high-k spacer width are optimized for high-performance digital applications. [ABSTRACT FROM AUTHOR]