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This brief presents a 10-Gb/s transmitter using a low-power one-stage 8:1 multiplexer. In the proposed transmitter, a differential current-steering output driver with a multiphase multiplexer architecture is used to alleviate speed limitations of the DRAM process. The current-steering output driver reduces the required output swing and increases the bandwidth of the multiplexer. The proposed multiplexer accomplishes not only high-speed operation but also low power dissipation by using a pseudo-nMOS configuration with one-stacked switches and reducing the short-circuit current of the gate driver in the multiplexer. The prototype of the transmitter using a 0.18- \mu\m CMOS technology achieves the power efficiency of 5.69 mW/Gb/s at the data rate of 10 Gb/s. [ABSTRACT FROM PUBLISHER]

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- \mu\m CMOS process, and a bit error rate of less than 10^-12 was achieved for a data rate up to 5.8 Gb/s using a 2^31 - 1 pseudorandom binary-sequence input. [ABSTRACT FROM PUBLISHER]