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With the wide application of reconfigurable design technology in the field of cryptography, the existing reconfigurable cryptography system can hardly meet the needs of high-speed communication and equipment miniaturization.Therefore, it is the goal of this paper to design a high performance reconfigurable processing architecture that can flexibly implement block cipher algorithms.Based on the reconfigurable array structure and the multi-launch mechanism, this paper proposes a reconfigurable multi-launch pipeline processing architecture to solve the problems of low throughput and low resource utilization of the reconfigurable cryptography system.This architecture is able to transmit multiple packets in parallel and pipeline processing, and has higher throughput and unit utilization, which greatly improves the algorithm performance of the reconfigurable system.Experiments show that the throughput of AES can reach 3.19 Gb/s under the operating frequency of 350 MHz.Compared with the single-launch structure, its performance improved by about 1.1 times.