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The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μA and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μs and the peak current efficiency is 99.8% at heavy loads. [ABSTRACT FROM AUTHOR]

Stacked mosfet structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked mosfet driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-μm process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 μA under no-load conditions. [ABSTRACT FROM AUTHOR]

In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulsewidth modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180° out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of $\pm$5 V. [ABSTRACT FROM PUBLISHER]

System-on-a-chip (SoC) applications require multiple power supply voltages with the features of low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for the single-inductor quad-output (SIQO) switching converter. This technique manages energy delivery to multiple outputs, facilitates fast transient response, and reduces cross-regulation simultaneously. Moreover, a level bypass detector (LBD) is used to overcome the limitation of significant loading differences among quad outputs in conventional designs because the PSP technique cantransfer additional energy to low-priority outputs to avoid overshoot voltage at high-priority outputs. Furthermore, voltage disturbance can be filtered out using two additional low-dropout regulators that operate as buffers cascaded at two low-priority outputs. Therefore, the SIQO converter that is fabricated in 40 nm CMOS technology satisfies the power requirements in portable electronics given its low cross-regulation of 0.2%, fast transient response of 15 \mu\s, and an output voltage ripple that is smaller than 30 mV. [ABSTRACT FROM AUTHOR]

Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital–analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 \muA. [ABSTRACT FROM AUTHOR]

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-µm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/µs saved 53% power. [ABSTRACT FROM AUTHOR]

A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm^2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/\mus as well as the improved MIPS performance by 5.6 times was achieved. [ABSTRACT FROM PUBLISHER]

Tradeoff between power efficiency and transient performance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching regulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which activates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary energy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Besides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient response can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-μm CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%. [ABSTRACT FROM AUTHOR]

The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 \mm^2 silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems. [ABSTRACT FROM PUBLISHER]