Search

Transistor scaling steadily approaches fundamental limits. Sustaining circuit reliability becomes an overwhelming challenge for foundries and their manufacturing processes. Therefore, early and rapid characterization of degradation effects impacting the circuits’ transistors becomes essential. Such degradation effects are caused by design-time variation due to manufacturing variability and/or run-time variation due to transistor aging. In this work, we are the first to employ brain-inspired HDC for circuit reliability. HDC is quickly emerging as an attractive light-weight machine-learning solution. Nowadays, it is mainly applied to bio-signal processing or language recognition. We bring the research of HDC to the next level by demonstrating how it can be applied to address the challenges in circuit reliability. This has far-reaching consequences due to the large savings achieved by 1) reducing the amount of training data and hence the development cycle, 2) removing the need to send the data to the cloud for model training, and 3) speeding up significantly the characterization and classification tasks due to the fast edge-inference. We demonstrate the viability of HDC using SRAM and other circuits as examples. HDC outperforms traditional machine learning methods, such as support vector machine or random forest, in accuracy and requires up to 20x fewer training samples. For a given budget of samples, HDC achieves a 4x smaller error. Our implementation and analysis are based on industrial $14 \;\mathrm{n}\mathrm{m}$ 14 n m FinFET fully calibrated with Intel measurements with respect to both transistor electrical characteristics as well as manufacturing variability. Open Source: Our framework including the algorithm implementation is available for the community to explore other algorithms and circuits at https://github.com/ML-CAD/HDC-Circuit-Reliability. [ABSTRACT FROM AUTHOR]

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points. [ABSTRACT FROM AUTHOR]

Self-heating (SH) is a phenomenon that can induce excessive heat inside the transistor channel. SH represents an emerging and serious concern, especially in advanced technology nodes, where excessive heat acting on elevated channel geometries will notably shift the critical transistor parameters (e.g., threshold-voltage $V_{\text {th}}$ and carrier mobility $\mu $). The underlying 3-D device structures (e.g., FinFET, nanowire, or nanosheet structures), along with newly employed materials such as silicon-germanium (SiGe), which show worse thermal conductivity than traditional materials, can considerably exacerbate SH. On top of that, quantum confinement, a phenomenon that becomes dominant at sub-10nm, further increases the intensity of SH. In this article, we are the first to explore SH effects from the perspective of hardware security, rather than the performance, reliability standpoints covered in state-of-the-art (SOTA) work. As proof of concept, we devise an SH-based hardware trojan (HT) that exploits the SH-induced $V_{\text {th}}$ change in 7-nm FinFET circuits. Leveraging $V_{\text {th}}$ -dependent reconfigurable logic, we design a reconfigurable HT payload that maliciously changes its functional behavior once the SH-induced $V_{\text {th}}$ change takes effect. Following SOTA work, we present a comprehensive modeling and analysis of SH effects at the device level and highlight its impact on transistor $V_{\text {th}}$. Next, we study how fabrication-time changes in the transistor doping and geometry can promote the SH-assisted degradation. We then describe various payload configurations for the proposed HT, quantify its overheads, and discuss its resilience against standard HT detection techniques. Finally, we demonstrate two case studies using the proposed HT, one to leak the secret key from a pipelined design of an advanced encryption standard (AES) circuit, and another to showcase denial-of-service for a Gaussian-blur filter circuit. Our work utilizes industry-standard models with parameters extracted from measurements and calibrated with experiments. Our results are obtained from meticulous study and optimization across the device-, circuit-, and system-levels. [ABSTRACT FROM AUTHOR]

Recent breakthroughs in Neural Networks (NNs) have made DNN accelerators ubiquitous and led to an ever-increasing quest on adopting them from Cloud to edge computing. However, state-of-the-art DNN accelerators pack immense computational power in a relatively confined area, inducing significant on-chip power densities that lead to intolerable thermal bottlenecks. Existing state of the art focuses on using approximate multipliers only to trade-off efficiency with inference accuracy. In this work, we present a thermal-aware approximate DNN accelerator design in which we additionally trade-off approximation with temperature effects towards designing DNN accelerators that satisfy tight temperature constraints. Using commercial multi-physics tool flows for heat simulations, we demonstrate how our thermal-aware approximate design reduces the temperature from 139 $^{\circ }$ ∘ C, in an accurate circuit, down to 79 $^{\circ }$ ∘ C. This enables DNN accelerators to fulfill tight thermal constraints, while still maximizing the performance and reducing the energy by around 75% with a negligible accuracy loss of merely 0.44% on average for a wide range of NN models. Furthermore, using physics-based transistor aging models, we demonstrate how reductions in voltage and temperature obtained by our approximate design considerably improve the circuit’s reliability. Our approximate design exhibits around 40% less aging-induced degradation compared to the baseline design. [ABSTRACT FROM AUTHOR]

HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits. [ABSTRACT FROM AUTHOR]

Ferroelectric Field-Effect Transistor (FeFET) is a promising future technology for non-volatile on-chip memories. It is rapidly attracting an ever-increasing attention from industry. The key advantage of FeFETs is full compatibility with the existing CMOS fabrication process beside their very low power consumption. To enable ultra-dense memories, 1-FeFET AND Arrays were proposed in which a memory cell is formed from merely a single FeFET. All access transistors, which are traditionally needed to operate memory cells, are removed. However, this imposes a new challenge of indirect write disturbances. Neighboring memory cells are indirectly degraded whenever a direct write operation occurs to a particular FeFET cell. Only recently the impact of such indirect disturbances on the FeFET reliability was experimentally investigated at device (i.e., transistor) level. However, to explore and properly judge the feasibility of 1-FeFET AND Arrays for on-chip memories, investigating only the reliability of individual cells is indeed insufficient. Bridging the gap between the device level and system (i.e., chip) level is inevitable. In the presence of indirect disturbances, the position of a write access within the array plays a key role, which is governed by the running workloads. In addition, whether the write operation flips the previously stored value or not also plays an important role with regards to reliability. Hence, running workloads, which determine not only the position of the memory cells to be written but also the values written to them, plays an essential role in determining 1-FeFET AND Array reliability over time. Therefore, studying the reliability of FeFETs only at the device level (as done in state of the art) is insufficient. In this work, we investigate, for the first time, the reliability of FeFET memories from device to system level. To achieve that, we develop a unified model capturing the impact of both indirect disturbances and direct writes on the reliability of FeFET cells. Our study at system level then employs the unified model in the context of application workloads. We investigate different array sizes, write voltages, write methods and a wide range of workloads using the example of CPU caches as an example of on-chip memory. We demonstrate that indirect write disturbances are the dominate effect degrading the reliability of FeFET memories. For most cells, it contributes over 90 percent to the overall induced degradation. This provides guidelines for researchers at both device and circuit level to optimize the FeFET reliability further while considering the hidden impact of indirect write disturbances. [ABSTRACT FROM AUTHOR]

Self-heating effect (SHE) is a major reliability concern in current and upcoming technology nodes due to its ability to increase the channel’s temperature of transistor and leading to degradations in the key electrical characteristics such as carrier mobility. In this brief, we study SHE in a full processor at the 7nm FinFET technology node. This is the first work to analyze the impact that executed workloads on top of processors have on stimulating SHE. As matter of fact, SHE in transistors is driven by the workload-induced switching activities. When it comes to evaluating SHE, state of the art typically assumes that the switching frequency ƒsw and operating clock frequency ƒclk of a circuit are the same, concluding that SHE is not a concern in digital circuits that operate in the GHz-range like processors. After analysis a wide range of workloads, our investigation revealed that the majority of transistors in the processor’s netlist exhibit a switching frequency in the kHz-range even though the processor’s clock is in the GHz-range. This is because that the majority of transistors are within the data paths and hence their switching is driven by the workload data and not by the clock itself. In addition, we also demonstrate for the first time the important role that the duty cycle (on-/off-ratio) induced by the running workload has on modeling SHE. All in all, the relatively low switching activities together with skewed duty cycles induce a wide variety in channel temperatures. Thus, highlighting the importance of considering the workload when studying SHE. [ABSTRACT FROM AUTHOR]

Voltage overscaling has received extensive attention in the last decade as an attractive paradigm for systems in which resulting timing errors and thus a loss in accuracy can be accepted in exchange for an increase in energy efficiency. At the same time, the delay of a circuit is, in turn, and in addition to voltage, also subject to temperature and aging. Existing work has largely studied voltage overscaling in isolation. This ignores interdependencies with temperature and aging, which can lead to wrong or misleading conclusions. In this work, we are the first to model the combined impact of voltage, temperature and aging on the delay of circuits towards investigating the actual existing trade-offs between efficiency and accuracy provided by voltage overscaling. We show that analyzing voltage in isolation overestimates timing errors and thus underestimates the voltage scaling potential. We further develop an approach that leverages interdependencies to optimize energy, delay and accuracy trade-offs. We precisely translate the individual and combined impact of voltage-, temperature-, and aging-induced delay increase into corresponding probability of error ($P_{error}$Perror). This reveals that the same amount of timing increase results in different error probabilities depending on the origin (i.e., voltage, temperature or aging). For the same timing increase, voltage reductions result in the smallest $P_{error}$Perror compared to temperature or aging, while also reducing temperature- and aging-induced delay increases themselves. This allows voltage reduction to be employed as an effective means to minimize delay, reduce energy and thus maximize efficiency under a given upper bound on error probability. We apply our approach to multipliers in GPUs exploring the trade-off between efficiency and accuracy. We demonstrate how only accounting for voltage scaling alone leads to a considerably larger $P_{error}$Perror (74% on average) than in reality. Our investigation also shows that for the same $P_{error}$Perror constraint, optimizing for combined voltage, temperature and aging effects results, on average, in 116% better energy-delay product (EDP) compared to state of the art. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the stress through the interconnection resources. By observing the impact of the signal probability on the aging of routing buffers, we enhance the synthesis flow as well as augment the proposed routing algorithm to converge the signal probabilities toward aging-friendly values. Experimental results over a set of industrial benchmarks and commerciallike FPGA architecture indicate the effectiveness of the proposed method with 64.3% reduction of stress duration in multiplexers and up to 45.2% improvement of the degradation of buffers. Altogether, the proposed method reduces the timing guardband by from 14.1% to 31.7%, depending on the FPGA routing architecture. [ABSTRACT FROM AUTHOR]

Circuit aging has become the major reliability concern in current and upcoming technology nodes. For instance, Bias Temperature Instability (BTI) leads to an increase in the threshold voltage of a transistor. That, in turn, may prolong the critical path delay of the processor and eventually may lead to timing errors. In order to avoid aging-induced timing errors, designers employ guardbands either with respect to voltage or frequency. State-of-the-art techniques determine a guardband type at the circuit level at design time irrespective from the running workload at the system level. Our investigation revealed that generated temperatures by a running workload have the potential to play a key role in determining the appropriate guardband type with respect to system performance. Therefore, we propose a paradigm shift in designing guardbands: to select the guardband types on-the-fly with respect to the workload-induced temperatures aiming at optimizing for performance under temperature and reliability constraints. Moreover, different guardband types for different cores can be selected simultaneously when multiple applications with diverse properties suggest this to be useful. Our dynamic guardband selection allows for a higher performance compared to techniques that employ a fixed (at design time) guardband type throughout. [ABSTRACT FROM AUTHOR]

DVFS-based boosting techniques have been widely employed by commercial multi-core processors, due to their superiority in improving the performance. Boosting, however, is particularly stressing circuits and hence it significantly contributes to an accelerated aging process. Circuit aging has become a real reliability concern because it leads to an increase in transistor threshold voltage that may cause timing errors as a result of higher delays in critical paths. Thus, high performance is desirable but it shortens the circuit lifetime through aging leaving a choice to trade-off. Besides well-known long-term aging effects, recent research also reported short-term aging effects. Our claim is that DVFS-based boosting techniques should consider both long- and short-term aging effects. This can be circumvented by wider timing guardbands. But that would be more expensive. The goal of this work is therefore to analyze and optimize boosting under specific consideration of long-term and short-term aging effects. As a result of our findings, we propose the first comprehensive aging-aware, yet efficient boosting technique. The employed aging-aware cell libraries in this work are publicly available at http://ces.itec.kit.edu/dependable-hardware.php. [ABSTRACT FROM AUTHOR]

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130 ◦ C and T = 25 ◦ C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits' maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant. Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130 ◦ C) compared to lower operating temperatures (T = 25 ◦ C). • Bias Temperature Instability (BTI) aging demonstrates substantial benifits concerning spatial power density and temperature. • Analysis leverages degradation-aware cell libraries for a 10-year aging perspective. • A Python-based power map generator facilitates the evaluation of power density. • Temperature assessment relies on Finite Element Method (FEM)-based thermal modeling. [ABSTRACT FROM AUTHOR]