31 results on '"Kaczer, Ben"'
Search Results
2. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
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Wu, Zhicheng, Franco, Jacopo, Vandooren, Anne, Arimura, Hiroaki, Ragnarsson, Lars-Ake, Roussel, Philippe, Kaczer, Ben, Linten, Dimitri, Collaert, Nadine, and Groeseneken, Guido
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ALUMINUM oxide ,COMPLEMENTARY metal oxide semiconductors ,CHARGE carrier mobility ,ELECTRON traps - Abstract
Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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3. On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in Iota Iota Iota V/High-k MOS Stack
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Putcha, Vamsi, Franco, Jacopo, Vais, Abhitosh, Sioncke, Sonja, Kaczer, Ben, Linten, Dimitri, and Groeseneken, Guido
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Technology ,Science & Technology ,InGaAs ,reliability ,Physics ,Engineering, Electrical & Electronic ,non-Arrhenius ,TRAPS ,Physics, Applied ,ENERGY ,capture-emission-time (CET) map ,Engineering ,Physical Sciences ,Bias temperature instability ,bivariate defect distributions - Abstract
© 1963-2012 IEEE. Operating temperature has a significant imp-act on the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ( Δ Neff) at operating condition typically shows an Arrhenius temperature dependence with EA 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77-373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture-emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total ΔV th measured in biaserature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. ispartof: IEEE TRANSACTIONS ON ELECTRON DEVICES vol:65 issue:9 pages:3689-3696 status: published
- Published
- 2018
4. Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET.
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Wu, Zhicheng, Franco, Jacopo, Truijen, Brecht, Roussel, Philippe, Kaczer, Ben, Linten, Dimitri, and Groeseneken, Guido
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CHARGE carrier mobility ,HOT carriers ,ON-chip charge pumps ,DENSITY of states ,ELECTRON mobility ,CARRIER density - Abstract
A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I – V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I – V modeling results: an universal mobility degradation normalization parameter N
it,ref = ~ 4.1 × 1011 /cm2 is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I – V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress. [ABSTRACT FROM AUTHOR]- Published
- 2021
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5. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration.
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Wu, Zhicheng, Franco, Jacopo, Vandooren, Anne, Roussel, Philippe, Kaczer, Ben, Linten, Dimitri, Collaert, Nadine, and Groeseneken, Guido
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TRANSISTORS ,CHARGE carrier mobility ,FIELD-effect transistors ,METAL oxide semiconductor field-effect transistors ,THIN film transistors ,ANNEALING of metals - Abstract
Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (V
BG ) is applied only during ON-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox ). Therefore, supplying an FBB during ON-state can be used to adjust device performance—as VBG modulates the channel current through Vth and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG – Vth (VBG ) is kept constant under different VBG ’s], the BTI reliability can be improved under FBB (due to a reduced Eox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation. [ABSTRACT FROM AUTHOR]- Published
- 2021
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6. Extraction of Statistical Gate Oxide Parameters From Large MOSFET Arrays.
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Stampfer, Bernhard, Simicic, Marko, Weckx, Pieter, Abbasi, Arash, Kaczer, Ben, Grasser, Tibor, and Waltl, Michael
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In modern MOS technologies continuous scaling of the geometry of transistors has led to an increase of the variability between nominally identical devices. To study the variability and reliability of such devices, a statistically significant number of samples needs to be tested. In this work we present a characterization study of defects causing BTI and RTN, performed on custom built arrays consisting of thousands of nanoscale devices. In such nanoscale devices, variability and reliability issues are typically analyzed for individual defects. However, the large number of measurements needed to extract statistically meaningful results make this approach infeasible. To analyze the large set of measurement data, we employ statistical distributions of the threshold voltage shifts arising from defects that capture and emit charge. This allows us to extract defect statistics using a defect-centric approach. Defect distributions are characterized for various gate, drain and bulk biases, and for two geometries to verify the methodology and to obtain statistics suitable for TCAD modeling and lifetime estimation. With the TCAD models we extrapolate the observed degradation of the devices. Finally, we investigate the influence of bulk and drain stress biases on the defects and observe that the impact of bulk bias on the device degradation is similar to that of the gate bias. In contrast, drain stress with drain biases up to −0.45V appears to be negligible for the investigated technology. Our measurements also clearly reveal that the overall BTI degradation is heavily dependent on the gate-bulk stress bias, while the extracted number of RTN defects seems to be independent on stress. [ABSTRACT FROM AUTHOR]
- Published
- 2020
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7. On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in IIIV/High- ${k}$ MOS Stack.
- Author
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Putcha, Vamsi, Franco, Jacopo, Vais, Abhitosh, Sioncke, Sonja, Kaczer, Ben, Linten, Dimitri, and Groeseneken, Guido
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METAL oxide semiconductor field-effect transistors ,ELECTRIC potential ,SILICON carbide ,SEMICONDUCTOR devices ,SEMICONDUCTORS - Abstract
Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]
- Published
- 2018
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8. Key Issues and Solutions for Characterizing Hot Carrier Aging of Nanometer Scale nMOSFETs.
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Duan, Meng, Zhang, Jian Fu, Ji, Zhigang, Zhang, Wei Dong, Kaczer, Ben, and Asenov, Asen
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METAL oxide semiconductor field-effect transistors ,NANOSTRUCTURED materials ,BAND gaps ,SILICON ,ELECTRIC fields - Abstract
Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nanodevices, there are a number of challenges for characterizing their HCA: the random charge–discharge of traps in gate dielectric causes “within-a-device-fluctuation (WDF),” making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nanodevices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation ( $\sigma )$ and mean value ( $\mu $ ). Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is a little information on the accuracy of the extracted $\sigma $ and $\mu $ . We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of ten traps per device, the extracted $\mu $ and $\sigma $ has an accuracy of ±14% and ±24%, respectively, with a 95% confidence. [ABSTRACT FROM PUBLISHER]
- Published
- 2017
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9. An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel.
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Ji, Zhigang, Zhang, Xiong, Franco, Jacopo, Gao, Rui, Duan, Meng, Zhang, Jian Fu, Zhang, Wei Dong, Kaczer, Ben, Alian, Alireza, Linten, Dimitri, Zhou, Daisy, Collaert, Nadine, De Gendt, Stefan, and Groeseneken, Guido
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METAL oxide semiconductor field-effect transistors ,COMPLEMENTARY metal oxide semiconductors ,INDIUM gallium arsenide ,QUANTUM wells ,ATOMIC layer deposition - Abstract
Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]
- Published
- 2015
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10. Predictive Hot-Carrier Modeling of n-Channel MOSFETs.
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Bina, Markus, Tyaginov, Stanislav, Franco, Jacopo, Rupp, Karl, Wimmer, Yannick, Osintsev, Dmitry, Kaczer, Ben, and Grasser, Tibor
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METAL oxide semiconductor field-effect transistors ,HOT carriers ,CHARGE carriers ,ELECTRON-electron interactions ,ELECTRON scattering - Abstract
We present a physics-based hot-carrier degradation (HCD) model and validate it against measurement data on SiON n-channel MOSFETs of various channel lengths, from ultrascaled to long-channel transistors. The HCD model is capable of representing HCD in all these transistors stressed under different conditions using a unique set of model parameters. The degradation is modeled as a dissociation of Si–H bonds induced by two competing processes. It can be triggered by solitary highly energetical charge carriers or by excitation of multiple vibrational modes of the bond. In addition, we show that the influence of electron–electron scattering (EES), the dipole-field interaction, and the dispersion of the Si–H bond energy are crucial for understanding and modeling HCD. All model ingredients are considered on the basis of a deterministic Boltzmann transport equation solver, which serves as the transport kernel of a physics-based HCD model. Using this model, we analyze the role of each ingredient and show that EES may only be neglected in long-channel transistors, but is essential in ultrascaled devices. [ABSTRACT FROM PUBLISHER]
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- 2014
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11. Interplay Between Statistical Variability and Reliability in Contemporary pMOSFETs: Measurements Versus Simulations.
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Hussin, Razaidi, Amoroso, Salvatore Maria, Gerrer, Louis, Kaczer, Ben, Weckx, Pieter, Franco, Jacopo, Vanderheyden, Annelies, Vanhaeren, Danielle, Horiguchi, Naoto, and Asenov, Asen
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METAL oxide semiconductor field-effect transistors ,POLYCRYSTALLINE silicon ,DOPING agents (Chemistry) ,SURFACE roughness ,THRESHOLD voltage - Abstract
This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions. [ABSTRACT FROM PUBLISHER]
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- 2014
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12. Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
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Kukner, Halil, Weckx, Pieter, Raghavan, Praveen, Kaczer, Ben, Catthoor, Francky, Van Der Perre, Liesbet, Lauwereins, Rudy, and Groeseneken, Guido
- Abstract
With deeply scaled CMOS technology, Bias Temperature Instability (BTI) has become one of the most critical degradation mechanisms impacting the device reliability. In this paper, we present the BTI evaluation of a single inverter gate covering both the PMOS and NMOS degradations in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. Thus, the BTI degradation is investigated due to the impact of 1) duty factor, 2) periodic clock-based and non-periodic random input sequences, 3) gate drive strength. The inverter is chosen due to its representativity of other CMOS logic gates. The applied BTI model is stochastic, and the device parameters are orthogonally generated by distributions. Results show 3% and 27% degradation shifts on the distribution mean and worst-case. In addition, it is shown that the near-critical paths with lower drive strength cells are more susceptible to the BTI degradation than the critical paths with higher drive strength cells. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
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13. Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits.
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Weckx, Pieter, Kaczer, Ben, Toledano-Luque, Maria, Raghavan, Praveen, Franco, Jacopo, Roussel, Philippe J., Groeseneken, Guido, and Catthoor, Francky
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TRANSISTORS , *SEMICONDUCTORS , *GAUSSIAN distribution , *SEMICONDUCTOR junctions , *STATIC random access memory - Abstract
This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
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14. Improved Channel Hot-Carrier Reliability in p-FinFETs With Replacement Metal Gate by a Nitrogen Postdeposition Anneal Process.
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Cho, Moonju, Arimura, Hiroaki, Lee, Jae Woo, Kaczer, Ben, Veloso, Anabela, Boccardi, Guillaume, Ragnarsson, Lars-Ake, Kauerauf, Thomas, Horiguchi, Naoto, and Groeseneken, Guido
- Abstract
Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with \N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high-k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG \sim VD/\2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
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15. Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates.
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Kukner, Halil, Khan, Seyab, Weckx, Pieter, Raghavan, Praveen, Hamdioui, Said, Kaczer, Ben, Catthoor, Francky, Van der Perre, Liesbet, Lauwereins, Rudy, and Groeseneken, Guido
- Abstract
In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
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16. Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits.
- Author
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Camargo, Vinicius V. A., Kaczer, Ben, Wirth, Gilson, Grasser, Tibor, and Groeseneken, Guido
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INTEGRATED circuit design ,TRANSISTORS ,QUANTITATIVE research ,SENSITIVITY analysis ,MATHEMATICAL models - Abstract
This paper presents an extensive statistical study on the impact of bias temperature instability (BTI) on digital circuits. A statistical framework for the evaluation of BTI at the electrical (SPICE) level, enhanced by an atomistic model for BTI, is introduced. This framework is then employed to perform the timing analysis of different combinational paths using cells from a given library, aiming to statistically model BTI at the higher abstraction level. A statistical static timing analysis (SSTA) method is then performed and the results are compared to detailed simulations using atomistic models based on experimental data. The comparison between the two methods shows that for large paths both methods converge to the same distribution for the delay while for short paths the delay distributions are different causing the SSTA method to generate misleading results. An analysis is then performed in order to understand and formalize the results. [ABSTRACT FROM AUTHOR]
- Published
- 2014
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17. NBTI Reliability of SiGe and Ge Channel pMOSFETs With \SiO2/\HfO2 Dielectric Stack.
- Author
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Franco, Jacopo, Kaczer, Ben, Mitard, Jerome, Toledano-Luque, Maria, Roussel, Philippe J., Witters, Liesbeth, Grasser, Tibor, and Groeseneken, Guido
- Abstract
Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]
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- 2013
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18. Energy Distribution of Positive Charges in Gate Dielectric: Probing Technique and Impacts of Different Defects.
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Hatta, Sharifah Wan Muhamad, Zhigang Ji, Jian Fu Zhang, Meng Duan, Wei Dong Zhang, Soin, Norhayati, Kaczer, Ben, De Gendt, Stefan, and Groeseneken, Guido
- Subjects
METAL oxide semiconductor field-effect transistors ,COMPLEMENTARY metal oxide semiconductors ,ELECTRONIC probes ,THRESHOLD voltage ,CONDUCTION bands ,DIELECTRIC thin films ,BAND gaps - Abstract
Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated. [ABSTRACT FROM AUTHOR]
- Published
- 2013
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19. SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI.
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Franco, Jacopo, Kaczer, Ben, Roussel, Philippe J., Mitard, Jérôme, Cho, Moonju, Witters, Liesbeth, Grasser, Tibor, and Groeseneken, Guido
- Subjects
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METAL oxide semiconductor field-effect transistors , *COMPLEMENTARY metal oxide semiconductors , *DIGITAL electronics , *LOGIC circuits , *ROBUST control - Abstract
We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness. [ABSTRACT FROM AUTHOR]
- Published
- 2013
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20. SiGe Channel Technology: Superior Reliability Toward Ultra-Thin EOT Devices—Part II: Time-Dependent Variability in Nanoscaled Devices and Other Reliability Issues.
- Author
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Franco, Jacopo, Kaczer, Ben, Toledano-Luque, María, Roussel, Philippe J., Kauerauf, Thomas, Mitard, Jérôme, Witters, Liesbeth, Grasser, Tibor, and Groeseneken, Guido
- Subjects
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FET switches , *THRESHOLD voltage , *METAL oxide semiconductor field-effect transistors , *ELECTRIC breakdown , *ELECTRIC discharges , *BREAKDOWN voltage - Abstract
The time-dependent variability of nanoscaled \Si0.45 \Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as \1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology. [ABSTRACT FROM AUTHOR]
- Published
- 2013
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21. Circuit Design-Oriented Stochastic Piecewise Modeling of the Postbreakdown Gate Current in MOSFETs: Application to Ring Oscillators.
- Author
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Martin-Martinez, Javier, Kaczer, Ben, Degraeve, Robin, Roussel, Philippe J., Rodriguez, Rosana, Nafria, Montserrat, Aymerich, Xavier, Dierickx, B., and Groeseneken, Guido
- Abstract
A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
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22. The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps.
- Author
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Grasser, Tibor, Kaczer, Ben, Goes, Wolfgang, Reisinger, Hans, Aichinger, Thomas, Hehenberger, Philipp, Wagner, Paul-Jürgen, Schanovsky, Franz, Franco, Jacopo, Toledano Luque, María, and Nelhiebel, Michael
- Subjects
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TEMPERATURE effect , *SWITCHING circuits , *COMPLEMENTARY metal oxide semiconductors , *DIFFUSION , *GATE array circuits , *METALLIC oxides , *STRAINS & stresses (Mechanics) - Abstract
One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction–diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction–diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area. [ABSTRACT FROM PUBLISHER]
- Published
- 2011
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23. Off-State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices.
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Griffoni, Alessio, Chen, Shih-Hung, Thijs, Steven, Kaczer, Ben, Franco, Jacopo, Linten, Dimitri, De Keersgieter, An, and Groeseneken, Guido
- Subjects
METAL oxide semiconductors ,LOGIC circuits ,HIGH voltages ,ELECTRIC discharges ,THYRISTORS ,SEMICONDUCTOR defects ,RELIABILITY in engineering ,ELECTRIC lines - Abstract
The off-state degradation of n-channel laterally diffused metal–oxide–semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an \n^+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both off-state and ESD reliability. [ABSTRACT FROM AUTHOR]
- Published
- 2011
- Full Text
- View/download PDF
24. NBTI Lifetime Prediction and Kinetics at Operation Bias Based on Ultrafast Pulse Measurement.
- Author
-
Zhigang Ji, Lin, L., Jian Fu Zhang, Kaczer, Ben, and Groeseneken, Guido
- Subjects
RELIABILITY in engineering ,INTEGRATED circuit design ,MANUFACTURING defects ,PICOSECOND pulses ,DIELECTRICS ,METAL oxide semiconductor field-effect transistors - Abstract
Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias V
g acceleration to reduce the test time, and the data were typically obtained from quasi-dc measurements. Recently, it has been shown that substantial recovery occurs during the quasi-dc measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can still be used. This work will show that the prediction based on the Vg acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%. [ABSTRACT FROM AUTHOR]- Published
- 2010
- Full Text
- View/download PDF
25. A New TDDB Reliability Prediction Methodology Accounting for Multiple SBD and Wear Out.
- Author
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Sahhaf, Sahar, Degraeve, Robin, Roussel, Philippe J., Kaczer, Ben, Kauerauf, Thomas, and Groeseneken, Guido
- Subjects
OXIDES ,STATISTICS ,DIELECTRICS ,ELECTRIC breakdown ,ELECTRIC discharges ,ELECTRICITY - Abstract
In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting breakdown (SBD) and post-SBD wear-out (WO) parameters measuring the time to hard breakdown (t
HBD ) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model includes SBD and WO. [ABSTRACT FROM AUTHOR]- Published
- 2009
- Full Text
- View/download PDF
26. Extraction of the Random Component of Time-Dependent Variability Using Matched Pairs.
- Author
-
Kaczer, Ben, Franco, Jacopo, Roussel, Philippe J., Groeseneken, Guido, Chiarella, Thomas, Horiguchi, Naoto, and Grasser, Tibor
- Subjects
TIME-dependent density functional theory ,SEMICONDUCTORS ,ELECTRON mobility ,DIELECTRICS ,GALLIUM nitride - Abstract
Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of matched pairs are discussed and the correlation between time-zero and time-dependent variances is formalized. [ABSTRACT FROM AUTHOR]
- Published
- 2015
- Full Text
- View/download PDF
27. Energy Distribution of Positive Charges in Al2O3GeO2/Ge pMOSFETs.
- Author
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Ma, Jigang, Zhang, Jian F., Ji, Zhigang, Benbakhti, Brahim, Zhang, Wei, Mitard, Jerome, Kaczer, Ben, Groeseneken, Guido, Hall, Steve, Robertson, John, and Chalker, Paul
- Subjects
ELECTRIC power distribution reliability ,ALUMINUM oxide ,METAL oxide semiconductor field-effect transistors ,CHARGE density waves ,ELECTRIC circuits ,LOGIC circuits - Abstract
The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3/GeO2/Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
- Full Text
- View/download PDF
28. Negative Bias Temperature Instability in p-FinFETs With 45^\circ Substrate Rotation.
- Author
-
Cho, Moonju, Ritzenthaler, Romain, Krom, Raymond, Higuchi, Yuichi, Kaczer, Ben, Chiarella, Thomas, Boccardi, Guillaume, Togo, Mitsuhiro, Horiguchi, Naoto, Kauerauf, Thomas, and Groeseneken, Guido
- Subjects
FIELD-effect transistors ,SILICON ,LOGIC circuits ,CHARGE density waves ,STRAY currents ,HIGH-k dielectric thin films - Abstract
Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45^\circ rotated devices compared with the 0^\circ rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45^\circ rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv—exhibited when transitioning from planar to FinFET architecture at 45^\circ rotation—plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45^\circ rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho [ABSTRACT FROM AUTHOR]
- Published
- 2013
- Full Text
- View/download PDF
29. Weibull slope and voltage acceleration of ultra-thin (1.1–1.45 nm EOT) oxynitrides
- Author
-
O'Connor, Robert, Degraeve, Robin, Kaczer, Ben, Veloso, Anabela, Hughes, Greg, and Groeseneken, Guido
- Subjects
- *
SILICON , *VOLTAGE regulators , *ELECTRIC insulators & insulation , *DIELECTRICS - Abstract
The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the
tbd distributions, and the voltage acceleration factor. High fieldtBD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes (β ), which improve reliability. The highβ values were investigated by monitoring the change inβ as gate current increased during CVS. We saw the Weibull slope change from ≈1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values ofβ . [Copyright &y& Elsevier]- Published
- 2004
- Full Text
- View/download PDF
30. Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
- Author
-
Kükner, Halil, Weckx, Pieter, Raghavan, Praveen, Kaczer, Ben, Catthoor, Francky, Van der Perre, Liesbet, Lauwereins, Rudy, and Groeseneken, Guido
- Subjects
- *
POWER transmission , *GATE array circuits , *ATOM trapping , *TEMPERATURE -- Mathematical models , *RELIABILITY in engineering , *COMPLEMENTARY metal oxide semiconductors - Abstract
Abstract: In deeply scaled CMOS technologies, Bias Temperature Instability (BTI) is one of the most critical degradation mechanisms impacting the device reliability. This study presents the BTI evaluation of gates covering both the PMOS and NMOS degradation in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. In this paper, the impact of (1) duty factor, (2) periodic clock-based and non-periodic random input sequences, (3) gate, and (4) drive strength to the BTI degradation are investigated. Statistical studies show a mean degradation of 3% and a worst-case of 27%. Moreover, the near-critical paths with lower drive strength cells are 3.7× more susceptible to BTI degradation than the critical paths with higher drive strength cells. Next, the relative degradations of the propagation delays for the well-known gates (i.e. INV, NAND, NOR, AOI) are presented. Under the same stress stimuli, degradations of the gate propagation delays differ by 4.5×. [Copyright &y& Elsevier]
- Published
- 2013
- Full Text
- View/download PDF
31. Charge trapping in MOSFETs with HfSiON dielectrics during electrical stressing
- Author
-
O’Connor, Robert, Hughes, Greg, Degraeve, Robin, and Kaczer, Ben
- Subjects
- *
ELECTRIC charge , *METAL oxide semiconductor field-effect transistors , *DIELECTRICS , *METAL oxide semiconductors - Abstract
Abstract: Hafnium silicate had been suggested as a possible ‘mid-k’ alternative to SiON as a gate dielectric for the 45 nm technology node. This work focuses on the shift in threshold voltage, the degradation in transconductance, and the sub-threshold swing during oxide stress. Analysis of these parameters reveals much about the trap generation mechanisms in the layers, as well as differences from SiON. The effect of the aspect ratio dimensions on post-breakdown device functionality is also discussed. [Copyright &y& Elsevier]
- Published
- 2005
- Full Text
- View/download PDF
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