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This brief introduces a 3-bit magnetic analog-to-digital converter (MADC) employing the NAND-SPIN based multi-bit device which has the same structure as the NAND-SPIN memory cell. By adjusting the physical shape of the heavy metal (HM) line, the all-in-one integrated NAND-SPIN device exhibits multiple switching thresholds which could quantify the input current into several states and store them into the corresponding Magnetic Tunnel Junctions (MTJs). In order to read data reliably, a read port is connected to each Spin Orbit Torque (SOT) MTJs so as to minimize Tunnel Magnetoresistance (TMR) degradation due to non-uniform heavy metal resistance. In addition, an HM size adjustment methodology is proposed to improve the conversion accuracy and switching reliability. Detailed micromagnetic simulation results show that the proposed MADC could achieve 5 $GHz$ sampling rate with only $0.068~pJ$ conversion energy, and in-memory conversion for higher bit resolution while provides the benefit of nonvolatility. [ABSTRACT FROM AUTHOR]

With the rapid increase of leakage currents, non-volatile memories have become competitive candidates in the next-generation computer architecture. Among them, STT-MRAM shows great promise in working memory with high density, high speed and tremendous endurance, etc. However, based on our investigations, the dynamic write power and read reliability are two critical challenges of STT-MRAM. In this work, we propose a synergistic pseudo-differential sensing (PDS) framework that employs device, circuit and architectural techniques to address these challenges. In specific, three design techniques, including cell cluster, asymmetric sensing amplifier and self-error-detection-correction, are proposed to implement the PDS framework. We show that the holistic device-circuit-architecture cross-layer co-design enables STT-MRAM to be utilized in the cache memory, benefiting from the improved density, reliability and energy-efficiency. Our experimental results show that the proposed PDS scheme improves the read margin by ∼35.6 percent, reduces the area, read latency, read energy, write latency and write power by ∼46.7, ∼9.8, ∼30.3, ∼2.3 and ∼31.1 percent respectively, compared with the typical 1T1MTJ cell structure for the cache capacity of 8 MB. In addition, the proposed PDS scheme reduces the dynamic energy by ∼32.9 percent and leakage energy by ∼830 percent, improves the IPC by ∼1.3 percent and miss rate by ∼36.9 percent respectively, compared with conventional SRAM based cache. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]