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The semiconductor manufacturing is one of the most sophisticated processes in modern industries. It contains hundreds of complex operations, and this makes semiconductor reliability a challenging task especially in recent years that integrated circuits (ICs) have been broadly used at much wider areas including the health cares, automotive, and aerospace applications, where safety is the major concern. To make things worse, due to the shorter product life cycles and severe competitions, time-consuming reliability tests become unacceptable. The industries are in urgent need of a fast and effective way to quickly assess reliability risks. Under all these stringent limitations and the high reliability targets, we propose a consolidated approach that consists of an efficient and effective reliability baseline (BL) management system and a test scheme developed based on sequential probability ratio test (SPRT). To ensure a trustworthy setting for the SPRT test scheme, we apply the Bayesian approach to continuously update the BL database. An integrated flow chart is introduced to elucidate our proposed methodology. It is the first time SPRT is applied on reliability risk assessments with two unknown parameters. Several actual cases from semiconductor arena are reported to demonstrate the merits and powers of our proposed methodology. From these real cases, as a side benefit, we show the wide applicability of our method, which does not limit to reliability but on yield and functionality checks as well. To facilitate the use of our method by field practitioners, we do the best to explain derivations in a plain manner and provide analysis codes in R (in Supplementary Material) to make our approach as portable as possible. [ABSTRACT FROM AUTHOR]

The effects of baking temperature on back-end-of-line (BEOL) reliability were explored on 28 nm technology node. We found that stress migration (SM) worse temperature showed up around 200 °C and apparent negative resistance (R) shifts appeared after baking at high temperatures. The Electromigration (EM) performance behaved the temperature dependence and the high baking temperature improved the main time-to-failure (TTF) distribution. Interlayer dielectric (ILD) time dependence dielectric breakdown (TDDB) performance was enhanced at low baking temperatures. [ABSTRACT FROM AUTHOR]

The NBTI (negative bias temperature instability) performance of 28 nm HfO 2 -based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements. [ABSTRACT FROM AUTHOR]

In this paper, we report electromigration (EM) reliability optimizations using highly efficient uniform design (UD). Considering the large error that results from using a single lifetime index, and the different EM failure modes, we introduce a new proportion index incorporating early failures to compensate for the shortage of using a single traditional intrinsic lifetime index in our Design of Experiments (DOE). Applying a supersaturated UD DOE, we greatly reduce (> 70\\% savings) the number of wafers used in experiments, comparing to the classical RSM design. This very economic experiment has successfully maximized EM lifetimes, which are more than 10 times longer, and without early failure, in a much shorter period of time. [ABSTRACT FROM PUBLISHER]

Yield and reliability susceptibility would become obvious with the increase in the complexity of manufacturing technology. Yield and reliability enhancement is always our pursuit. However, tradeoffs between yield and reliability, or between Fab and assembly house, are often observed during the technology development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new technology, some practical experiences on solving tradeoffs in semiconductor manufacturing are reported; a generic procedure to handle the tradeoff problem is proposed, and the effectiveness was also proved. Early detection capability, baseline knowledge management, fully understanding customers' requirements, and effectively consolidating all parties' efforts are considered to play key roles in the procedure. It is believed that such a procedure can be also applied to solve the tradeoff problem in other industries. [ABSTRACT FROM AUTHOR]

The limitation of the trend test in SPC is reviewed. The current Nelson's run test for the six or seven consecutive increasing or decreasing points cannot detect non-monotonic increasing or decreasing trend that is frequently encountered in industries. This paper proposes the reverse arrangement test (RAT) to replace the current SPC trend test rule in order to detect both non-monotonic and monotonic increasing or decreasing trends. The theory of RAT is reviewed and we point out the errors in the tables from a well-known and most frequently referenced paper on RAT. The corrected tables of accumulated probabilities for each total reverse arrangement for N = 3 to 12 are presented. The false alarm rate from RAT is verified with excellent accuracy by 108 data points simulating stable normal distributed process. Real examples from the semiconductor manufacturing illustrate that 7 non-monotonic increasing points can be detected by RAT with the same false alarm rate as for the 6 monotonic increasing trend, while sometimes none of the current WECO and Nelson's rules can detect such abnormal pattern. Applications of RAT in IC SPC and WLRC (Wafer Level Reliability Control) show RAT is much more powerful than conventional monotonic trend tests in detecting nonconformance. [ABSTRACT FROM AUTHOR]

A method is proposed in this paper to determine whether a product, a component, or a system in reliability life testing has a longer lifetime than the other. We propose two indices to compare reliability. The comparison is also distribution-free; i.e., it does not require the assumption on the lifetime distributions. A comparability index that is derived by integrating the weighted difference between the reliability functions of the two groups under comparison is named the "Better or Worse" (BOW) index. The second comparability index that is derived by calculating the overlapping area under the two distributions in comparison is named "Reliability Comparability" (RC) to quantify the degree of similarity between the two distributions. These two new indices are compared with the conventional methods currently used in the IC industries. Practical applications in lifetime-type reliability comparison are also illustrated in this paper. [ABSTRACT FROM AUTHOR]