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We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low- ${k}$ interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technology node. We show that Ru and Co fills can significantly reduce resistance at narrow pitches. At 12 nm half-pitch, line and via resistance can be lowered by up to 36% and 75%, respectively, by replacing Cu with barrierless Ru fill; by using hybrid Cu metallization with Co via-prefill, at 12 nm half-pitch via resistance can be lowered by up to 42% in 87° tapered vias and up to 52% in chamfered vias. As far as capacitance is concerned, Ru fill can enable interconnect schemes without dielectric liner. In this case, the line capacitance can be substantially reduced by using linerless replacement low- ${k}$ or air-gap schemes, whose benefits become more significant at narrow pitches, when one accounts for low- ${k}$ sidewall damage in conventional low- ${k}$ schemes and takes these as a reference. [ABSTRACT FROM AUTHOR]

Graphene interconnects are being considered as a promising candidate for beyond CMOS applications, thanks to the intrinsic higher carrier mobility, lower aspect ratio and better reliability with respect to conventional Cu damascene interconnects. However, similarly to Cu, line edge roughness can seriously affect graphene resistance, something which must be taken into account when evaluating the related performance benefits. In this letter, we present a model for assessing the impact of edge scattering on the resistance of graphene interconnects. Our model allows the evaluation of the total mean free path in graphene lines as a function of graphene width, diffusive scattering probability and edge roughness standard deviation and autocorrelation length. We compare our model with other models from literature by benchmarking them using the same set of experimental data. We show that, as opposed to the considered models from literature, our model is capable to describe the mobility drop with scaling caused by significantly rough edges. [ABSTRACT FROM AUTHOR]

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step. [ABSTRACT FROM PUBLISHER]

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-of-line (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric \kappa -value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a $4\times $ process margin and suffers from 50% parametric yield loss. The required guardband for litho-etch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is $6\times $ higher than the critical dimension control. For trench patterning using spacer-defined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%. [ABSTRACT FROM PUBLISHER]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

This paper analyzes the impact of the interconnect variation at the system level in terms of clock frequency based on a fast and efficient system-level variation-aware design methodology. Various types of interconnect variations are compared, such as the critical dimension for line/core and spacer, etch, chemical mechanical polishing (CMP), and overlay variations. The $3 \sigma $ values for these independent variation values are extracted from various fabrication processes, including the litho-etch-litho-etch (LELE) double patterning, self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). The results indicate that the impact of the interconnect variation on the clock frequency increases for a processor at a smaller technology node, especially for the CMP variation. For the impact of the combination of five sources of interconnect variations, the processor using the SADP performs the best. The overlay variation and the spacer variation have a larger impact on the LELE double patterning and the SAQP patterning techniques. Up to 8% and 16% of the frequency drops are observed based on $1\times $ and $2\times $ of the default $3 \sigma $ values, respectively. [ABSTRACT FROM PUBLISHER]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

Ruthenium has emerged as a promising candidate to substitute Cu as the interconnect metallization in future technology nodes. Here, we demonstrate area scaling of Ru wires down to cross-sectional areas of 33 nm2 through subtractive patterning by using a metal-spacer patterning technique. The wires were characterized by physical as well as electrical measurements and demonstrate low resistivity, between 20 and $35~\mu \Omega $ cm for cross-sectional areas between 175 and 33 nm2. [ABSTRACT FROM AUTHOR]