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In this paper, we present a fully adaptive routing algorithm for 3D stacked mesh, called 3D-FAR. This algorithm utilizes two, two, and four virtual channels along the X, Y, and Z dimensions, respectively. It allows packets to take any shortest paths between the source and destination routers. 3D-FAR divides the network into four disjoint subnetworks. To improve the fault-tolerant capability of the network, packets are able to switch between subnetworks in an ascending order. In this paper, we also propose a fault-tolerant algorithm for 3D mesh network, called 3D-FT. This method is discussed both for tolerating faulty routers and links in the network. For tolerating faulty routers, only the shortest paths are taken while for tolerating faulty links, the non-minimal paths are used only when the source and destination routers are located in the same dimension with a faulty link between them. 3D-FT utilizes a distributed monitoring and management technique to distribute the fault statuses among the surrounding routers. [ABSTRACT FROM PUBLISHER]

Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results show that Honeycomb topology outperforms Mesh by at least 25.9%, 54.2% and 30.0% in these three aspects. [ABSTRACT FROM PUBLISHER]

Congestion-aware routing algorithms can improve network throughput by avoiding packets to be routed through congested areas. In this paper, we propose a minimal/non-minimal routing algorithm to alleviate congestion in the network by making use of all available paths between sources and destinations. The simplicity of the proposed algorithm provides a cost and power efficient solution for Networks-on-Chip while the high degree of adaptive ness, achieved by using an additional virtual channel along the Y dimension, leads to an increased performance. In this method, different restrictions are imposed on the use of each virtual channel, so that the prohibited turns in one virtual channel are permitted in the other one. By fully exploiting of the eligible turns in the network, a large number of output channels can be provided by the proposed method. Based on this method, a packet is routed along the non-minimal path when the neighboring routers in the minimal path are congested. [ABSTRACT FROM PUBLISHER]

Three-dimensional (3D) integration is a viable design paradigm to overcome the existing interconnect bottleneck in integrated systems and enhance system power/performance characteristics. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, stacked mesh 3D NoC architecture was proposed. However, this architecture suffers from naive and straightforward hybridization between NoC and bus media. In this paper, an efficient hybridization scheme is presented to enhance system performance, power consumption, and area of stacked mesh 3D NoC architectures. By utilizing a routing rule called LastZ the proposed hybridization scheme offers many advantages investigated in detail to emphasize the significant achievements. Our extensive simulations with synthetic and real benchmarks, including an integrated videoconference application show that compared to a typical 3D NoC-Bus Hybrid Mesh architecture, our hybridization scheme achieves significant power, performance, and area improvements. [ABSTRACT FROM PUBLISHER]

The emerging three-dimensional integrated circuits (3D ICs) offer a promising solution to mitigate the barriers of interconnect scaling in modern systems. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, 3D NoC-Bus Hybrid mesh architecture was proposed. Besides its various advantages in terms of area, power consumption, and performance, this architecture has a unique and hitherto previously unexplored way to implement an efficient system-wide monitoring network. In this paper, an integrated low-cost monitoring platform for 3D stacked mesh architectures is proposed which can be efficiently used for various system management purposes. The proposed generic monitoring platform called ARB-NET utilizes bus arbiters to exchange the monitoring information directly with each other without using the data network. As a test case, based on the proposed monitoring platform, a fully congestion-aware adaptive routing algorithm named AdaptiveXYZ is presented taking advantage from viable information generated within bus arbiters. Our extensive simulations with synthetic and real benchmarks reveal that our architecture using the AdaptiveXYZ routing can help achieving significant power and performance improvements compared to recently proposed stacked mesh 3D NoCs. [ABSTRACT FROM PUBLISHER]

Congestion occurs frequently in Networks-on-Chip when the packets demands exceed the capacity of network resources. Congestion-aware routing algorithms can greatly improve the network performance by balancing the traffic load in adaptive routing. Commonly, these algorithms either rely on purely local congestion information or take into account the congestion conditions of several nodes even though their statuses might be out-dated for the source node, because of dynamically changing congestion conditions. In this paper, we propose a method to utilize both local and non-local network information to determine the optimal path to forward a packet. The non-local information is gathered from the nodes that not only are more likely to be chosen as intermediate nodes in the routing path but also provide up-to-date information to a given node. Moreover, to collect and deliver the non-local information, a distributed propagation system is presented. [ABSTRACT FROM PUBLISHER]

while Networks-on-Chip have been increasing in popularity with industry and academia, it is threatened by the decreasing reliability of aggressively scaled transistors. This level of failure has architectural level ramifications, as it may cause an entire on-chip network to fail. Traditional fault-tolerant routing algorithms can overcome the faulty links or routers by rerouting packets around faulty regions. These approaches increase the packet latency and create congestion around the faulty region. In this paper, we present a novel fault-tolerant method that is able to route packets through shortest paths in the presence of faulty links, as long as a path exists. Although the same idea can be applied to a network with any number of virtual channels, we utilize two virtual channels to tolerate all one and two faulty links. Finally, the method is extended to support multiple faulty links by fully utilizing all allowable turns in the network. [ABSTRACT FROM PUBLISHER]

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5X6 crossbar is used for the proposed architecture which requires one more 5X1 multiplexer without increasing the critical path delay of the router as compared to the 5X5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead. [ABSTRACT FROM PUBLISHER]

Three-dimensional integrated circuits (3D ICs) offer greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, 3D NoC-Bus Hybrid mesh architecture was proposed. This architecture provides a seemingly significant platform to implement an integrated low-cost system-wide monitoring network. In this paper, a generic monitoring and management platform called ARB-NET is presented. Based on the ARB-NET monitoring platform, a fully congestion-aware adaptive routing algorithm named AdaptiveXYZ is provided which takes advantage from viable information generated within the monitoring network. In addition, we address both the power and thermal issues of a stacked mesh 3D network on chips using AdaptiveXYZ routing. To this end, a thermal model of a 3D stacked NoC system in a modern flip-chip package is developed. Thermal and power analysis are performed in order to investigate the impact of the proposed adaptive routing from the power and thermal perspectives. Our experiments with a videoconference encoder as a real application show significant power, performance and peak temperature improvements compared to a typical stacked mesh 3D NoC. [ABSTRACT FROM PUBLISHER]

One of the main factors limiting the performance of Networks-on-Chip is congestion. Routing algorithms perform an important role in distributing the traffic load over the network by providing alternative routing paths. The major parts of research works avoid congestion by considering the traffic condition in the forward paths and delivering packets through less congested paths. However, they do not consider the impact of the router arbitration in traffic distribution. On the other hand, traditional methods usually consider the traffic at the node level rather than a region level. In this paper, we propose a method named Dual Congestion Awareness (DuCA) which involves the congestion information about forward paths in the routing decision and backward paths in the router arbitration. DuCA can efficiently use the traffic information to transmit packets through less congested areas (using congestion information about forward paths) and steer traffic from highly congested regions to low congested areas (using congestion information in backward paths). Finally, DuCA is a region-based approach, providing a wider view of the network traffic. [ABSTRACT FROM PUBLISHER]

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead. [ABSTRACT FROM PUBLISHER]