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3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified with improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present two generalized routing algorithms for different reduced vertical channel density topologies, which can maintain the performance of the NoC and critically improve the utilization of TSV. The experiments for simulation were done in SystemC-RTL which can achieve more flexibility and maintain the cycle accuracy. From the experimental results in aspects of execution time, average throughput, system interconnect and TSV energy consumption, and TSV utilization, 50% vertical channel density topologies achieved the best trade-off for the given constrains. [ABSTRACT FROM PUBLISHER]

3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also raises the question when the higher implementation costs are really profitable. To answer this question, for a lot of different cases, a framework was developed for simulating 3-dimensional (3D) NoCs, which provides results that are close to real applications and implementations. The framework is highly adaptable in terms of traffic scenarios, available memory, network size (including manual Through-Silicon-VIA (TSV) settings), routing algorithm, chip size and implementation technology. As the complexity of this framework increased in both, environment setup and available information, it was decided to build a graphical user interface (GUI) for an easy access to it. This user interface consists of a lucid configuration interface for generating the traffic scenarios and adjusting all necessary parameters for running a successful simulation. It further provides a front-end for observing the network during the running simulation. To give the user a good notion about the networks behavior, information about the processing elements (PEs) current state, the buffer utilization and the link utilization is displayed in a 2-dimensional (2D) and 3D model of the network. To check if predefined conditions to the energy budget and distributed memory demands are met, an automatically generated post simulation report summarizes all the gained information. This report includes the systems configuration, the buffer fill level, interconnect energy consumption and link utilization for each node and in total. [ABSTRACT FROM PUBLISHER]