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Smart door locks pose a large number of threats such as network attacks. Its storage area and power of cipher are severely limited because the wireless nodes of smart door locks are mostly battery‐powered. Therefore, effective security solutions are urgently needed. In this paper, a new lightweight block cipher with low power named LPHD is proposed to ensure the security of the master control chip of the smart door lock terminal. We design a scheme of low power S‐box and construct the two‐stage permutation layer (TP structure) suitable for LPHD by filtering the sets of 8‐bit permutations. LPHD proposes a variant of the 8‐branch generalized Feistel structure (GFS) to realize that the bits of all branches are affected in one encryption round. The problem of slow diffusion in the standard Feistel structure is solved. The key schedule adopts the nonlinear design and reuses the encryption process of LPHD. It improves the security of the cipher and reduces hardware overhead. Moreover, we evaluate the hardware implementation and security of LPHD. The results show that LPHD for the unified encryption and decryption circuits requires only 1276 Gate Equivalents (GEs) and 1.914 μ$$ \upmu $$W on UMC 0.18 μ$$ \upmu $$m, which is better than other lightweight block ciphers such as SKINNY, PRESENT, and IVLBC. In summary, LPHD provides sufficient security for the master control chip of the smart door lock terminal. [ABSTRACT FROM AUTHOR]

Lightweight block ciphers are important for implementing security services on constrained devices today. In this paper, we propose a novel ultra-lightweight block cipher DULBC based on a dynamic SPN structure. The round function of DULBC adopts an unfixed F-function and a bit-based permutation. The choice of the F-function depends on 2 bits of the round keys. This means the encryption process of the cipher is uncertain and its security is greatly improved. Also, a strong 4 × 4 S-box with fewer logic gates is proposed, which costs low hardware resources and ensures excellent performances. We have conducted FPGA implementation and ASIC implementation on DULBC. The throughput of DULBC-80/128 is 555.03/443.84 Mbps and the area of the 16-bit serial architecture of DULBC-80/128 is 1075/1351 GEs, respectively. DULBC is secure and efficient according to our experiments and comparisons. • A novel lightweight block cipher with dynamic structure to improve security and privacy. • Performance of the 4 × 4 S-box with fewer logic gates is even better compared with the isomorphic S-boxes. • High throughput and low area consumption in hardware implementation. [ABSTRACT FROM AUTHOR]