Search

Although metal/ferroelectric/semiconductor tunnel junctions have been attracting widespread interest as next-generation memory devices, only limited effort has been devoted so far to quantitatively address their current–voltage characteristics and their achievable memory window. In this article, we show experimental data on template Pt/BaTiO3/Nb:SrTiO3 tunnel junctions confirming, first of all, that large memory windows can be achieved in these devices when the switching of the electric polarization in the ferroelectric layer moves the substrate between an accumulation and a depletion condition. Besides, by measuring the current–voltage curve of the devices quickly after the set/reset pulses used for polarization switching, the importance of considering the detrimental effects of the large depolarization fields in the ferroelectric layer when assessing the device memory window is demonstrated. The experimental data are, then, reproduced by a model for electron transport through the junction accounting for both drift/diffusion and distributed tunneling in the semiconductor. The model allows to catch a comprehensive physical picture of device operation and represents a powerful tool for the design and optimization of ferroelectric tunnel junctions with semiconductor electrodes.

We show that a Meyer-Neldel (MN) regime, usually reported for disordered materials, is found in state-of-the-art monocrystalline Si MOSFETs. This unexpected result is explained via device simulation in terms of the self-consistency between the mobile charge and the device electrostatics. The dependence on device parameters is then discussed, showing that neglecting this effect can lead to interpretation errors for data evaluated at low activation energies.

This paper presents a physics-based compact model able to describe the time dynamics of the erase operation in three-dimensional NAND Flash strings exploiting gate-induced drain leakage at the selector to increase the string potential. The model accurately reproduces all the main phases of the erase operation and allows to calculate the threshold voltage transient arising from hole injection into and electron emission from the gate stack of the memory cells, accounting for the correct cylindrical geometry of the string. Thanks to its simple structure, the model is suitable for parametric analyses aiming at optimizing the string structure and the operating waveforms from the standpoint of the erase performance.

Hong et al. [1] presented an analytical solution for the electrostatic potential in undoped cylindrical MOSFETs, which was then employed within a well-known Pao-Sah integral to yield the device current. This same analytical solution and drain current calculation were presented in 2016 [2] , but such work was not referenced by Hong et al. [1] .

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.

This paper presents a detailed simulation analysis of the impact of 3-D electrostatics and atomistic doping on the variability of the random telegraph noise (RTN) time constants in nanoscale MOS devices. Results on a template decananometer Flash cell show that both the effects contribute to a large statistical dispersion of the capture/emission time constants of oxide traps placed at the same distance from the silicon surface, mainly due to nonuniform channel inversion. The statistical dispersion has an orders-of-magnitude increase when moving from the on-state to the subthreshold cell regimes and has major implications on the spectroscopic investigation of RTN traps, as will be discussed in Part II of this work.

We present a self-consistent 2-D quantum-mechanical model for charge distribution in cylindrical gate-all-around devices with computation of the gate tunneling current. The validity of 1-D approximations for the charge and the gate current is discussed, assessing the validity of a previously proposed analytical approximation for the tunneling current in the Fowler-Nordheim regime.

This paper presents a detailed investigation of the impact of cycling time and temperature on the threshold-voltage instability arising from damage recovery during data retention on nanoscale nand Flash. Statistical results from the programmed state show that instabilities result, on average, in a threshold-voltage loss, which increases logarithmically with the time elapsed since the end of cycling. The slope of the logarithmic behavior strongly depends on the electric field during data retention, the cycling dose, and the probability level at which the shift of the array cumulative distribution is monitored. Increasing the cycling time and temperature corresponds, instead, to an equivalent delay of the instant at which the first read operation on the array is performed. The delay is studied for a large variety of cycling and retention conditions, extracting the parameters required for a universal damage-recovery metric for nand.

This paper investigates the statistical variability sources affecting the program operation of nanoscale charge-trap memories. Using the 3-D TCAD model presented in Part I of this work, featuring a Monte Carlo simulation approach to deal with discrete traps in the storage layer, atomistic doping in the substrate, and granular electron injection from the substrate to the storage layer, we consider the effect of three main variability sources impacting charge-trap memory programming: 1) the statistical process ruling electron injection and trapping; 2) the fluctuation in the number and position of the trapping sites; and 3) the statistical distribution of the threshold-voltage shift induced by stored electrons in presence of percolative substrate conduction. We show that the first variability source plays the dominant role in determining the statistical dispersion of cell threshold voltage during the program operation.

This paper presents experimental evidences of the granular electron injection during channel hot-electron programming of NOR Flash memories. The statistical process ruling the discrete charge transfer from the substrate to the floating gate is shown to introduce a fundamental spread contribution to the programmed threshold-voltage distribution obtained by the staircase algorithm, determining its ultimate accuracy. However, the actual precision in the control of cell threshold-voltage during programming is shown to be quite far from this fundamental limitation due to random telegraph noise effects. Moreover, the scaling trend of the electron injection statistics and the random telegraph noise limitation to the accuracy of the programming algorithm shows that the latter will continue to represent the most severe constraint for the next nor technology nodes.

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.

This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.

This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations.

An accurate method for the evaluation of boundary integrals in semiconductor device modeling is presented. The method is compared against more common algorithms and can achieve both high accuracy and low computational time. The range of applications is extremely wide, including contact currents and charges, carrier quantum probability fluxes, and heat fluxes

This paper analyzes solutions to improve the program/erase (P/E) window for nanocrystal (NC) memory cells, by means of the model presented in our previous work . The limited threshold voltage (V/sub T/) window typically observed in the Fowler-Nordheim (FN) programming regime for NC memories was shown to be a direct consequence of the lack of any conduction and /spl epsi/ mismatch between the tunnel and the interpoly-oxide at steady-state. This condition can be avoided when tunnel oxide conduction is due to direct tunneling, but to assure sufficiently short P/E times very thin oxides are required, sacrificing cell nonvolatility. The use of alternative materials for interpoly dielectric, gate and NC is investigated. Finally, barrier engineering is presented as a valid way to improve the available V/sub T/ window.

This paper presents a detailed study of the program/erase (P/E) dynamics under uniform tunneling for nanocrystal (NC) memories. Calculating the potential profile and the tunneling currents across the dielectric barriers, we evaluate NC charging and discharging transients during P/E operations. The calculated P/E windows and times compare well with experimental data for memory cells with different oxide thicknesses. The model accounts for the typical features of threshold voltage (V/sub T/) shift as a function of applied gate voltage, and can be used as a valuable tool for optimizing the cell geometry and parameters for maximum performance.

Two-dimensional quantum-mechanical simulations of nonoverlapped MOS devices are presented, and validated through comparison against experimental data. Simulations are used to highlight the electrical characteristics of these devices, explore their design tradeoffs and optimize the performance with respect to the nonoverlap length. Simulations show that a minimum switching time is always achieved by adopting a nonoverlapped structure if the MOS device is operating properly. This approach can effectively improve the performance of decananometer MOSFETs.

In this paper, a full two-dimensional (2-D) quantum mechanical (QM) device simulator for deep submicron MOSFETs is presented. The model couples a 2-D Schrodinger-Poisson solver with a semiclassical transport model. The validity of the proposed model is first tested against a QM model for transport, developed as a benchmark. Then, QM effects on nanoscale MOSFETs performance are quantitatively addressed and discussed. It is shown that QM effects strongly influence the device performance, namely subthreshold slope drain-induced barrier lowering and short-channel effects. These results show that full QM simulations will become a mandatory issue for nanoscale MOSFETs modeling and design.

We present a semi-analytical model for the description of charge trapping and detrapping phenomena occurring during cycling and idle periods in NAND Flash memories. The model is based on a statistical distribution of detrapping time constants that is affected by the composition of cycles and idle periods and accounts for charge discreteness, statistical charge capture and emission and statistical distribution of the threshold-voltage shift due to single detrapping events. The model can reproduce the experimental data under different conditions and allows to develop and monitor accelerated schemes able to mimic realistic on-field usage of the memory device.

This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.

This paper presents a numerical investigation of the random telegraph noise amplitude in nanoscale MOS devices based on the statistical impedance field method. This method allows a strong reduction of the computational burdens required for the calculation of the amplitude statistics with respect to conventional Monte Carlo models based on the numerical implementation of microscopic differences on the simulated device structure, allowing the exploration of lower probability levels. Despite a rather good estimation of the amplitude statistics, however, the method results in relevant inaccuracies when looking at the single Monte Carlo samples, due to the linear approximations involved.

We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.

This paper investigates the validity of distributed-cycling schemes on scaled Flash memory technologies. These schemes rely on the possibility to emulate on-field device operation by increasing the cycling temperature according to an Arrhenius law, but the assessment of the activation energy that has to be used on scaled technologies requires a careful control of the experimental tests, preventing spurious second-order effects to emerge. In particular, long gate-stresses required to gather the array threshold voltage (V T ) map are shown to give rise to parasitic V T -drifts, which add to the V T -loss coming from damage recovery during post-cycling bake. When the superposition of the two phenomena is taken into account, the effectiveness of the conventional qualification schemes relying on a 1.1 eV activation energy is fully confirmed at the 45 nm NOR node.

This paper presents a detailed compact-modeling investigation of the string current in decananometer nand Flash arrays. This investigation allows, first of all, to highlight the role of velocity saturation, low-field mobility, and drain-induced barrier lowering on the string current versus read voltage characteristics. Results are validated on a 41-nm technology for different positions of the selected cell along the nand string, different pass voltages, and different array background patterns. The effect of cycling on the string current is then investigated by means of postcycling bake experiments, showing that the impact of charge trapping/detrapping and interface state generation/annealing varies as a function of the read current level. Compact-modeling results display that, at low read currents, charge trapping/detrapping represents the main damage mechanism for the cells, while interface states come into play for read currents close to the string saturation level via mobility degradation.

We present a detailed semi-analytical investigation of the transient dynamics of gate-all-around (GAA) charge-trap memories. To this aim, the Poisson equation is solved in cylindrical coordinates, and a modification of the well-known Fowler-Nordheim formula is proposed for tunneling through cylindrical dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering a quite extended range of gate biases and times. Finally, the model is used for a parametric analysis of the GAA cell, highlighting the effect of device curvature on both program/erase and retention.

This paper presents a detailed investigation of the performance of a double-verify algorithm for accurate programming of deca-nanometer NAND Flash memories. In order to minimize the programmed threshold-voltage distribution width in presence of discrete and statistical electron injection, a weakened programming step is applied to cells if their threshold voltage falls between a low- and a high-program-verify level during incremental step pulse programming. Clear improvements are shown with respect to the single-verify case, with minimal burdens on programming time and complexity.

This paper presents a detailed investigation of charge-trap memory programming by means of 3-D TCAD simulations accounting both for the discrete and localized nature of traps and for the statistical process ruling granular electron injection from the substrate into the storage layer. In addition, for a correct evaluation of the threshold-voltage dynamics, cell electrostatics and drain current are calculated in presence of atomistic doping, largely contributing to percolative substrate conduction. Results show that the low average programming efficiency commonly encountered in nanoscaled charge-trap memory devices mainly results from the low impact of locally stored electrons on cell threshold voltage in presence of fringing fields at the cell edges. Programming variability arising from the discreteness of charge and matter will be addressed in Part II of this paper.

This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design.

This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale NAND Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.

This work investigates the variability effects on the threshold voltage distribution of deca-nanometer NAND Flash memories. Different sources of variability have been considered, evaluating their impact on the neutral, programmed and erased distributions. A compact model that is able to account for the variability effects on the array performance and reliability is presented and used. Monte Carlo simulations have been employed to analyze the contributions of variability when technology nodes scale down and to compare the intrinsic variability with the electron injection statistical fluctuations. A good agreement with experimental data is reached, opening the application of the proposed methodology to investigate the reliability impact of variability on future technology nodes.

This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.

This paper presents a scaling analysis of the statistical distribution of the threshold voltage shift (ΔVT) obtained by electron storage in nitride memories, considering both its average and standard deviation. For fixed density of trapped charge, the average ΔVT decreases as a consequence of fringing fields, not predictable by any 1-D simulation approach. Moreover, the distribution statistical dispersion increases with technology scaling due to a more sensitive percolative substrate conduction in the presence of atomistic doping and 3-D electrostatics. The impact of these effects on device performance is then highlighted, showing that the accuracy of the staircase programming algorithm can be reduced further from the limitation given by the electron injection statistics during programming. The impact of electron storage in the nitride on random telegraph noise instabilities is also investigated, showing that, despite single cell behavior may be modified, negligible effects result at the statistical level.

This letter presents a comparison of two different variability sources for data retention of nanoscale NAND Flash memories: the neutral threshold-voltage spread and the electron-emission statistics from the floating gate. Referring to fresh cells programmed to the same threshold-voltage level, the effect of the previous dispersion contributions on the data retention transients of a memory array is evaluated. Both effects are shown to result into a broadening of the array threshold-voltage distribution with time, but a quantitative assessment clearly shows that the neutral threshold-voltage spread dominates over the electron-emission spread, revealing that cell-to-cell parameter variations represent the major source of variability for data retention in nanoscale NAND Flash memories.

This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.

In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al 2 O 3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al 2 O 3 charge storage modifies program and erase saturation level particularly when higher Al 2 O 3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al 2 O 3 trapping. Moreover, Al 2 O 3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.

This work investigates for the first time chargegranularity effects during channel hot-electron programming of NOR Flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOR technologies ranging from 180 to 45 nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.

This letter presents a detailed investigation of the random telegraph noise (RTN) effects on the threshold-voltage distribution of flash memory arrays programmed by the staircase algorithm. RTN is shown to introduce an exponential tail above the program verify level when considering the cell threshold voltage that ends the program operation. In addition, when a subsequent read operation is considered, a clear exponential tail is shown to appear even below the program verify level. We present a simple analysis that is able to predict the threshold-voltage distribution width accounting for both these enlargement contributions, defining practical formulas for the programming accuracy as a function of the staircase step amplitude and the RTN distribution.

This paper presents an analytical investigation of the spatial and energetic position of the traps responsible for threshold voltage random telegraph fluctuations in a metal-oxide-semiconductor device. Assuming a stationary trap-filling condition as a result of the application of a constant gate bias, a simple formula is obtained to identify the oxide region where traps having an arbitrary probability to change their state between two subsequent time instants are located. Results are extremely important for the statistical spectroscopic analysis of random telegraph noise sources.

We present a detailed analytical modeling for the constant-current Fowler-Nordheim program operation of NAND flash memories, able to describe both the average transient of the cell threshold voltage and its statistical spread due to the granular nature of the electron current flowing through the cell tunnel oxide. We analytically investigate the electron-injection process, highlighting that the steepness of the tunneling current versus floating-gate voltage characteristics and the control-gate to floating-gate capacitance give the field feedback factor, determining the average number of injected electrons at which the injection process becomes sub-Poissonian. Finally, we show that cell scaling will reduce the achievable accuracy of the program algorithm, due to the reduction in the number of electrons controlling cell state.