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The analysis of retention characteristics is essential for reliability assessment of any type of flash memory. A high-k (HK) material in the Interpoly dielectric (IPD) stack is known to improve the program-erase characteristics and makes the control oxide thicker for better retention time; however, it also brings-in defects along with it, creating undesirable charge loss path that plays a significant role in retention. Accurate modeling of this leakage process is important for optimizing the architecture that is less prone to oxide defects and exhibiting improved charge retention. In this paper, we present a physical model considering all possible charge leakage mechanisms that include inelastic tunneling through multiple traps in addition to direct tunneling (DT). The trap capture process is modeled as an inelastic process from nanocrystal (NC) to trap state, while the trap-to-trap tunneling is calculated by Bardeen's Transfer Hamiltonian approach. The trap emission process and DT from the spherical NC are modeled by computing the lifetime of quasi-bound states with very small decay widths in the finite-element setup. We show that a single trap model in HK cannot explain the retention characteristics. We propose a new asymmetric IPD structure that show significant improvement in retention time. [ABSTRACT FROM AUTHOR]

The program/erase process in floating gate (FG) flash memory devices is modeled by considering sequential quantum tunneling of electrons and taking into account quantum confinement in the channel and FG. We precisely determine location of quasi-bound or decaying quantum states in the inversion layer and in FG comprising a nanocrystal (NC) layer, and compute their lifetime by finding the complex eigenenergy of the resonance transmission problem. Self-consistent solutions to Poisson and Schrödinger equations are obtained for the quantum states of electrons in the inversion layer of MOS devices, and subsequently, sequential Fowler–Nordheim tunneling current to the spherical NCs is obtained using finite-element method considering open boundary conditions. The method described here is capable of determining the tunneling current accurately for arbitrary potential profiles, and can be applied for composite tunnel dielectric stacks. Our results show good agreement with the experimental data for high- $k$ interpoly dielectric flash memory devices. [ABSTRACT FROM PUBLISHER]