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Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which will result in misidentification. In this paper, a novel deep learning model called adaptive balancing generative adversarial network (AdaBalGAN) is proposed for the defective pattern recognition (DPR) of wafer maps with imbalanced data. In addition, a categorical generative adversarial network is improved to generate simulated wafer maps in high fidelity and classify the patterns with high accuracy for all defective categories. Taking consideration of the various learning abilities of the DPR model for different patterns into account, an adaptive generative controller is designed to balance the number of samples of each defective type according to the classification accuracy. The experiment results indicated that the proposed AdaBalGAN model outperforms conventional models with higher accuracy and stability for the DPR of wafer maps. Further results of comparative experiments revealed that the proposed adaptive generative mechanism can enhance and balance the recognition accuracy for all categories in the DPR of wafer maps. [ABSTRACT FROM AUTHOR]

The semiconductor manufacturing is one of the most sophisticated processes in modern industries. It contains hundreds of complex operations, and this makes semiconductor reliability a challenging task especially in recent years that integrated circuits (ICs) have been broadly used at much wider areas including the health cares, automotive, and aerospace applications, where safety is the major concern. To make things worse, due to the shorter product life cycles and severe competitions, time-consuming reliability tests become unacceptable. The industries are in urgent need of a fast and effective way to quickly assess reliability risks. Under all these stringent limitations and the high reliability targets, we propose a consolidated approach that consists of an efficient and effective reliability baseline (BL) management system and a test scheme developed based on sequential probability ratio test (SPRT). To ensure a trustworthy setting for the SPRT test scheme, we apply the Bayesian approach to continuously update the BL database. An integrated flow chart is introduced to elucidate our proposed methodology. It is the first time SPRT is applied on reliability risk assessments with two unknown parameters. Several actual cases from semiconductor arena are reported to demonstrate the merits and powers of our proposed methodology. From these real cases, as a side benefit, we show the wide applicability of our method, which does not limit to reliability but on yield and functionality checks as well. To facilitate the use of our method by field practitioners, we do the best to explain derivations in a plain manner and provide analysis codes in R (in Supplementary Material) to make our approach as portable as possible. [ABSTRACT FROM AUTHOR]

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations. [ABSTRACT FROM AUTHOR]

Reliability assessment is very important in semiconductor manufacturing, and we need to setup and maintain an efficient and effective reliability baseline (BL) management system to, for example, assess reliability risks, to dispose impacted lots, and to release equipment. To achieve these goals, we propose a corresponding flow and pinpoint the critical points to establish and maintain reliability BLs. To provide insights to readers by actual cases on reliability BL analyses and applications, we setup and analyze the BLs for the electric-field acceleration factor and activation energy of gate oxide, the gate voltage exponent of device Negative Bias Temperature Instabilities (NBTI), and the parameters of interconnect model for current density and activation energy. We also find the enriched reliability BL database does benefit line excursion disposition, process optimization, quicker judgment on the reliability impacts of nonconformance, feasibility studies of process changes, faster tool releases, risk assessments of common reliability tests, and earlier root cause identifications of abnormality by narrowing down failure mechanisms. [ABSTRACT FROM AUTHOR]

The limitation of the trend test in SPC is reviewed. The current Nelson's run test for the six or seven consecutive increasing or decreasing points cannot detect non-monotonic increasing or decreasing trend that is frequently encountered in industries. This paper proposes the reverse arrangement test (RAT) to replace the current SPC trend test rule in order to detect both non-monotonic and monotonic increasing or decreasing trends. The theory of RAT is reviewed and we point out the errors in the tables from a well-known and most frequently referenced paper on RAT. The corrected tables of accumulated probabilities for each total reverse arrangement for N = 3 to 12 are presented. The false alarm rate from RAT is verified with excellent accuracy by 108 data points simulating stable normal distributed process. Real examples from the semiconductor manufacturing illustrate that 7 non-monotonic increasing points can be detected by RAT with the same false alarm rate as for the 6 monotonic increasing trend, while sometimes none of the current WECO and Nelson's rules can detect such abnormal pattern. Applications of RAT in IC SPC and WLRC (Wafer Level Reliability Control) show RAT is much more powerful than conventional monotonic trend tests in detecting nonconformance. [ABSTRACT FROM AUTHOR]