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The semiconductor manufacturing is one of the most sophisticated processes in modern industries. It contains hundreds of complex operations, and this makes semiconductor reliability a challenging task especially in recent years that integrated circuits (ICs) have been broadly used at much wider areas including the health cares, automotive, and aerospace applications, where safety is the major concern. To make things worse, due to the shorter product life cycles and severe competitions, time-consuming reliability tests become unacceptable. The industries are in urgent need of a fast and effective way to quickly assess reliability risks. Under all these stringent limitations and the high reliability targets, we propose a consolidated approach that consists of an efficient and effective reliability baseline (BL) management system and a test scheme developed based on sequential probability ratio test (SPRT). To ensure a trustworthy setting for the SPRT test scheme, we apply the Bayesian approach to continuously update the BL database. An integrated flow chart is introduced to elucidate our proposed methodology. It is the first time SPRT is applied on reliability risk assessments with two unknown parameters. Several actual cases from semiconductor arena are reported to demonstrate the merits and powers of our proposed methodology. From these real cases, as a side benefit, we show the wide applicability of our method, which does not limit to reliability but on yield and functionality checks as well. To facilitate the use of our method by field practitioners, we do the best to explain derivations in a plain manner and provide analysis codes in R (in Supplementary Material) to make our approach as portable as possible. [ABSTRACT FROM AUTHOR]

Yield and reliability susceptibility would become obvious with the increase in the complexity of manufacturing technology. Yield and reliability enhancement is always our pursuit. However, tradeoffs between yield and reliability, or between Fab and assembly house, are often observed during the technology development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new technology, some practical experiences on solving tradeoffs in semiconductor manufacturing are reported; a generic procedure to handle the tradeoff problem is proposed, and the effectiveness was also proved. Early detection capability, baseline knowledge management, fully understanding customers' requirements, and effectively consolidating all parties' efforts are considered to play key roles in the procedure. It is believed that such a procedure can be also applied to solve the tradeoff problem in other industries. [ABSTRACT FROM AUTHOR]

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions. [Copyright &y& Elsevier]