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This paper presents a novel approach to make high-performance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm²/V · s (NMOS) and 128 cm²/V · s (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration. [ABSTRACT FROM AUTHOR]

As the semiconductor industry strives toward wafer postprocessing and three-dimensional integration, a demand has arisen for high-quality thin films deposited at temperatures below 400°C. In this work, we present SiO2 films deposited at near room temperature, using a multipolar electron cyclotron resonance (ECR) plasma source, introducing the SiH4 gas by using a high-velocity jet of silane diluted in helium. The electrical properties were studied under varying deposition parameters, such as gas flow rate, deposition pressure, and postdeposition and postmetallization annealing processes. At a low pressure, low SiH4 flow and high helium flow, device-quality SiO2 layers were obtained after a deposition combined with a 5 mm postmetallization annealing at 400°C. These layers exhibited a refractive index of 1.46, an O/Si ratio of 2, an interface trap density in the order of 1011 cm2 eV-1, an oxide charge density down to 1010 cm2, and a breakdown field up to 11 MV/cm. They are thus suitable as a gate dielectric in a thin-film transistor. [ABSTRACT FROM AUTHOR]

Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4 · 10-4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n+ and p+ contacts, by confining the injected carriers in an SOI peninsula. With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps. [ABSTRACT FROM AUTHOR]

Remarkably strong infrared light emission was recently observed from silicon p+-n diodes. In several publications a causal relation is proposed between the larger-than-expected light intensity and the existence of lattice damage around the junction. In this letter, we present direct experimental evidence that lattice damage is in fact detrimental to the efficiency of light emission of silicon LEDs. The experiments call for a revision of the explanation for strong light emission in this type of devices. [ABSTRACT FROM AUTHOR]