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An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility! velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations. [ABSTRACT FROM AUTHOR]

Temperature dependence of hole mobility in Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs was investigated up to 473 K in order to examine the advantage in mobility at temperatures in operating very-large-scale-integrated circuit (VLSI) devices, which are significantly higher than room temperature. High-temperature operation and hole-mobility enhancements are demonstrated up to 473 K for the SGOI-pMOSFETs, which were fabricated by the Ge-condensation technique. The observed drain-current enhancements at 473 K against that of a reference SOI-pMOSFET were almost the same as those at 300 K. Phonon-limited mobility, which ultimately dominates mobility at high temperatures, was extracted by analyzing the temperature dependence of mobility down to 23 K. The extracted phonon- limited mobility exhibited enhancement factors of 12 and 5.5 at 473 K for SGOI devices with Ge fractions of 0.92 and 0.59, respectively, suggesting that such strained-SGOI channels retain the advantage in mobility at elevated temperatures in operating the VLSI devices. [ABSTRACT FROM AUTHOR]

We have developed the source-heterojunction- MOS-transistor (SHOT), a novel high-speed MOSFET with relaxed-SiGe/strained-Si heterojunction source structures for quasi-ballistic or full-ballistic transistors. Using the band-offset energy at the source SiGe/strained-Si heterojunction, high velocity electrons can be injected into the strained-Si channel from the SiGe source region. For the first time, we have experimentally demonstrated that the transconductance is enhanced in SHOT for high applied drain voltage, compared to that of strained- and conventional silicon-on-insultor MOSFETs. We have also shown that the transconductance enhancement in SHOT depends on both the gate drive and the drain bias. [ABSTRACT FROM AUTHOR]

We have newly developed (110)-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on (110)-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on (110)-surface SO! wafers. We have demonstrated that the electron and the hole mobility enhancement of (110)-surface strained-SO! devices amounts to 23% and 50%, respectively, against the mobilities of (110)surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of (110)-surface strained-SO! MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the (110)-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a (110)-surface Si. As a result, the (110)-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-oninsulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%∼40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO2-Ge interface. [ABSTRACT FROM AUTHOR]

Abstract: Dislocation behaviors in SiGe-on-insulator (SGOI) layers during the Ge condensation process are systematically studied by employing transmission electron microscopy, X-ray diffraction, Raman spectroscopy and secondary ion mass spectroscopy, in order to obtain insights into sufficient relaxation of SGOI layers with good crystal quality. It is found that misfit dislocations (MDs) are generated in the ramping up process in Ge condensation, whereas they disappear and threading dislocations (TDs) are generated after the oxidation process. This TD generation is attributable to the fact that the MDs were fragmented into dislocation half-loops and then rose to the SiGe surface. Thus, suppression of the rising motion is a key to fabricating high-quality SGOI substrates by the Ge-condensation technique. [Copyright &y& Elsevier]