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Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]

The article reports that the excellent electrical properties of single-walled carbon nanotubes (SWCNT) make them the most promising candidate for creating transistors on a scale smaller than can be achieved with silicon. A field-effect transistor (FET), which is the basic component of present computer circuitry, has been demonstrated based on individual SWCNTs. This achievement would demonstrate that SWCNTs can be used as a basis for electronics, similar to the way silicon wafers are currently used. A ring oscillator is the ultimate test for new materials in high-frequency ac applications and for evaluating their compatibility with conventional circuit architectures. In a CMOS inverter, both an n-type FET and a p-type FET are needed to realize a basic logic function. An extra inverter stage, which eliminates interference between the measurement setup and the oscillator operation, follows the ring oscillator portion to allow for the signal to be read by a spectrum analyzer.