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In tunnel field-effect transistors, trap-assisted tunneling (TAT) is one of the probable causes for degraded subthreshold swing. The accurate quantum-mechanical (QM) assessment of TAT currents also requires a QM treatment of phonon-assisted tunneling (PAT) currents. Therefore, we present a multi-band PAT current formalism within the framework of the quantum transmitting boundary method. An envelope function approximation is used to construct the electron-phonon coupling terms corresponding to local Fröhlich-based phonon-assisted inter-band tunneling in direct-bandgap III-V semiconductors. The PAT current density is studied in up to 100 nm long and 20 nm wide p-n diodes with the 2- and 15-band material description of our formalism. We observe an inefficient electron-phonon coupling across the tunneling junction. We further demonstrate the dependence of PAT currents on the device length, for our non-self-consistent formalism which neglects changes in the electron distribution function caused by the electron-phonon coupling. Finally, we discuss the differences in doping dependence between direct band-to-band tunneling and PAT current. [ABSTRACT FROM AUTHOR]

Field‐effect transistors (FETs), using transition metal dichalcogenides (TMD) as channels, have various types of interfaces, and their characteristics are sensitively changed in temperature and electrical stress. In this article, the effect of fast cyclic thermal stress on the performance of FETs using TMD as a channel is investigated and introduced. The Al2O3 passivation layer is deposited onto the TMD channel by atomic layer deposition process, and the hysteresis decreases and the direction changes from clockwise to counterclockwise. Applying cyclic thermal stress that rapidly heats and cools by 90 K in a 20 s cycle increases and decreases drain current repeatedly as charges move between the TMD channel and the interface traps. As cyclic thermal stress is applied, permanent interfacial damage occurs, resulting in increased interface trap density at the bottom and decreased hysteresis. These experimental results are also shown through technology computer‐aided design simulations. In addition, series resistance and mobility attenuation factor increase due to the concentration of the conduction paths at the bottom of the channel. [ABSTRACT FROM AUTHOR]

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices. [ABSTRACT FROM AUTHOR]

Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor nearby the gate dielectric. For an Si n-type TFET, the energy quantization in the conduction band is found to suppress the TAT through the interface-region traps by several orders of magnitude and delay the TAT through bulk traps nearby the gate dielectric with several hundreds of millivolts. The trap levels closer to the conduction band were found to be the most efficient for TAT in this n-TFET. The FIQC onset voltage shift in TAT through bulk taps is found to be smaller than the band-to-band tunneling (BTBT) shift, enhancing the effective SS degradation in TFETs. We therefore show that it is equally important to include the FIQC effect when calculating TAT as when calculating BTBT generation rates. [ABSTRACT FROM PUBLISHER]