Search

Abstract: We have calculated a bit-error-rate (BER) of Josephson latching drivers using the Monte-Carlo simulations taking into account the thermal noise at the Josephson junctions. The latching driver under investigation is composed of parallel 8-junction stacks and a SQUID input gate. We have optimized the structure of the SQUID input gate based on the BER simulation to get larger bias margins with acceptable BER. We have shown that the bias margins of the latching driver with a 3-junction SQUID input gate are better than that using a 2-junction SQUID input gate. The high-speed measurement of the Josephson latching driver confirms the validity of the BER based optimization. We have obtained the BER lower than 10−12 at 5GHz and 10−5 at 10GHz in the Josephson latching driver with the 3-junction SQUID input gate by the high-speed test. [Copyright &y& Elsevier]

We have developed essential components for most of microarchitectures based on the single-flux-quantum (SFQ) logic. The circuit under test is composed of two registers, an ALU and a control unit, and made up of about 540 cells, 1600 Josephson junctions on 1.5 × 2.4 mm area. We have obtained the correct results by a sequence of several instructions, in which two integers are written into the registers with the LOAD and COPY operations, and then execute the ADD operation. Some of their functions were tested at both low and high frequencies. As a result, we found that the designed components could work at 15 GHz for the designed bias current and up to 18 GHz for higher bias currents. [Copyright &y& Elsevier]