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Conventionally, a linear feedback shift register (LFSR) constitutes linear sets of sequences with predictable periods, which are considered vulnerable to intruders. Besides, an LFSR limits the sequences of scan-for-test patterns. This work introduces a private key, which is a collection of keywords, to program the feedback coefficients and initial states of the LFSR, where each keyword modulates the LFSR with a different polynomial of the same degree. That is, each polynomial generates a linear set of sequences. Consequently, the aggregate polynomial has a set of unpredictable and nonlinear sequences with high statistical randomness. The keyword, which holds the coefficients and initial states of the LFSR, can be managed in a few bits and stored in first-in first-out memory array. HSPICE simulations for 90 nm CMOS technology verify the functionality and speed of the proposed programmable feedback shift register (PFSR) of size 16-bit with 64 keywords. Results show a clock speed of 500 MHz with a power consumption of 73 µW and transistor count of 37,593, wherein the overall period has 4,194,240 unpredictable nonlinear sequences that surpass most LFSR structures. The PFSR can be suited for ASIC and reconfigurable HDL synthesis for efficient stream cipher and scan-for-test applications. [ABSTRACT FROM AUTHOR]

In this work, the circuit for unsigned integer restoring division divides each bit in one clock cycle, resulting in total delay cycles equal to the number of bits (n) plus an extra cycle for the final result. Thus, the proposed n-bit division circuit has an access time of (n+1) clock cycles. The hardware cost includes a subtractor and six registers, aligned with a two-phase clocking system. The novelty lies in the shift register, which shifts to the left during the high phase and restores data during the low phase of the clock. Although there are two phases of operations, the subtractor completes a full cycle for computation. As a result, the subtractor's delay time determines the clock period. The control unit is a simple ring shifter triggered at the clock's low phase. The simulation results obtained from synthesized HDL and HSPICE at 90 nm TSMC technology validate the circuit's functionality and characteristic feature of a performance rate of O(n). Using a standard CMOS library component, the 32-bit arithmetic divider requires 33 ns to produce exact Quotient and Remainder values. The circuit operates at a 1 GHz clock cycle and consumes a power of 752 µW. The total number of transistors used in this circuit is 8,860. [ABSTRACT FROM AUTHOR]

We propose an adaptive learning machine-based branch predictor -- the shadow dynamic finite state machine (SDFSM) -- that enables more accurate branch predictions by learning unique branching patterns through a self-modifying technique. SDFSM states represent branch pattern bits. If a state mispredicts a branch, the state is swapped with its shadow state, which represents the correct branching pattern bit. Therefore, the prediction accuracy can reach 100% if the number of states matches a branch's pattern length. When compared to a 2-bit saturating counter using bimodal branch predictors, the SDFSM decreases average misprediction rates by 18.3%, with individual decreases as high as 55%. [ABSTRACT FROM AUTHOR]