Search

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates. [ABSTRACT FROM AUTHOR]

The novel design of asymmetric single-ended ten-transistor SRAM bit-cell (SE 10T-SRAM) using gate-all-around (GAA) carbon nanotube (CNT) FETs-based GAA CNT-GDI method along with dual-chirality technique for CNTs, the asymmetric write-assist and built-in read-assist schemes in the presence of more saving area and less energy consumption is suggested for portable/mobile multimedia applications. Based on the analytical-compact model, an equation for calculating write-static margin (WSNM) is presented by expressing the degree of dependence of the metric on the power supply voltage variation for the suggested bit-cell structure. The results of extensive simulations to evaluate the proposed bit-cell in single and multi-array structures indicate better static/dynamic noise margins, less sensitivity to process, voltage and temperature (PVT) variations, improvement of basic parameters in the presence of contact length changes, more noise-immunity with scalability at cell supply voltage, and better results in other comprehensive figure of merits (FoMs) parameter compared to nanotechnology-based counterpart circuits with the same number of transistors in the 16 nm technology node. Also, evaluating the proposed structure in the presence of changes in the contact length parameter of other transistors as a contact length sizing-level solution, indicating the achievement of an improved structure in the basic parameters such as static noise margin, power consumption, and energy-delay product (EDP) parameter compared to the default structure with a minimum-sizing contact length. Finally, in order to use the proposed bit-cell in a real application, the suggested structure for storing images based on quick response (QR) code is examined with a link between MATLAB and synopsys H-SPICE simulator tools based on suggested algorithm. The results demonstrate that the suggested bit-cell is with more appropriate and significant results in terms of comprehensive FoMs, in which the evaluations concerning the appropriate accuracy in pixel-by-pixel storage of images based on the peak signal-to-noise ratio (PSNR) and the mean structural similarity index measure (MSSIM) metrics, compared to other well-known counterpart schemes confirms the superiority of the proposed design. Hence, the proposed design can be used for various areas regarding multimedia device applications. [ABSTRACT FROM AUTHOR]

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales. In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter. Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance. [ABSTRACT FROM AUTHOR]