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Abstract: Further device scaling below the 65nm node required the introduction of metal gates/high-k layers. This paper discusses the etching approaches for patterning TiN/Mo, TiN/MoO x and TiN/MoO x N y layers used in poly-silicon metal gate stacks. We found that for these Mo based layers, the dry etching using any Cl2/O2 ratio provoked a severe isotropic etching. HBr gas was used as a key component for controlling side-walls passivation. The MoO x and MoO x N y layers were more prone to lateral attack compared to Mo due to the intrinsic stoichiometric oxygen. A good selectivity towards the substrate was obtained using high O2 flows in Cl2/O2/HBr mixtures. Etching of the TiN layer was carried out with Ar/Cl2. This process was tuned by adding HBr depending on the metal gate stack, which suggests that TiN etching is highly influenced by the Mo layer nature (TiN/Mo, TiN/MoO x and TiN/MoOxN y ). We have also compared the complete gate stack pattering characteristic when an oxide or an amorphous carbon hard mask has been used for pattern definition. [Copyright &y& Elsevier]

Abstract: This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90nm on a 6T-SRAM cell. The target fins consist of straight structures (40nm height and 17nm of critical dimension) patterned on a 22nm node with 90nm fin pitch. The patterning stack consists of 70nm of amorphous carbon as a hard mask with 25nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32nm node with 124nm fin pitch was no longer functional for patterning fins on a 22nm node with 90nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17nm of critical dimension on 90nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability. [Copyright &y& Elsevier]

Abstract: We report on gate patterning development for the 45nm node and beyond. Both poly-Si and different metal gates in combination with medium-k and high-k dielectrics have been defined. Source/drain silicon recess has been characterized for different stacks, yielding optimised processes for all investigated. Using hardmask based etching allowed us to produce sub-20nm poly-Si and metal gates. Implementation of advanced metal gate patterning in already developed multi-gate field effect transistors (MuGFET) devices has been demonstrated. [Copyright &y& Elsevier]