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Compositionally graded InAlAs buffers grown by metal–organic chemical vapor deposition are impaired by phase separation occurring at In content higher than 35%. Phase separation results in rough epilayers with poor crystalline material quality. By introducing low temperature grown InGaAs interlayers in the compositionally graded InAlAs buffer, the surface roughness decreases, allowing a grading of up to In 0.60 Al 0.40 As without any phase separation occurring. This composite buffer is applied to fabricate a 200 mm diameter InP-on-Si virtual substrate with a threading dislocation density around 1 × 10 8 cm −2 .

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafers, two issues have to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and results in unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with the addition of diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is that the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer onto a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate can be realized.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafer, two issues need to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and create unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with additional diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer to a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate is realized.

One effective approach to reduce the cost of GaN devices is to use 200 mm-diameter and 725 μm-thick p-Si substrates. We demonstrated RF and power GaN-on-Si HEMTs on small pieces of samples from 200 mm wafers using Au-contained process. f T /$f_{\max}$ of 36/33 GHz were achieved in 0.25 μm gate RF devices and breakdown voltage (BV off )>1200V was achieved in power devices. 200 mm wafers were fabricated using CMOS-compatible process and devices with BV off >850 V were achieved.

We demonstrate the influence of the arsine partial pressure (p(AsH3)) on the quality of a GaAs layer grown on Ge substrate by metal organic chemical vapor deposition. The GaAs quality improves with p(AsH3) used during the 100 nm thick GaAs buffer layer. By growing a GaAs buffer layer at 630 °C with p(AsH3) of 5 mbar, we obtain a smooth GaAs layer with a root mean square roughness of 4.7 Å. This GaAs layer does not contain anti-phase boundaries. With these optimized growth parameters, we fabricate a virtual GaAs substrate on a 200 mm silicon wafer as a first step towards the integration of III–V devices on silicon., National Research Foundation of Singapore

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (–OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of –OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of –OH groups from the ambient. This process results in defect-free bonded wafers. NRF (Natl Research Foundation, S’pore) Published version

An approach for heterogeneous integration of InGaAs MOSHEMTs and Si-CMOS is proposed and a high quality multi-layer transfer process is demonstrated in 200 mm wafer scale. Heterostructures for In0.30Ga0.70As MOSHEMTs were grown using MOCVD on 200 mm Si substrates with record low threading dislocation density of eff ) of ∼4900 cm2/Vs at sheet electron density (N) of 3 × 1012 cm−2 was achieved which is record among InxGa 1 -xAs (x T ) of ∼60 GHz was extracted for 150 nm channel length MOSHEMTs.

A method to integrate III-V compound semiconductors (e.g., GaN HEMT, InGaN LED, InGaAs HEMT or AlGaInP LED) and Si-CMOS on a common Si substrate is demonstrated. The Si-CMOS layer from SOI wafer is temporarily held on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. Additional III-V/Si substrates with different materials and structures can be integrated on the same piece of Si-CMOS+III-V/Si substrate by stacking another III-V/Si substrate before the handle wafer is removed. Through this method, integration of Si-CMOS with more than one type of III-V materials on a single Si platform can be realized (e.g., CMOS/InGaAs HEMT/GaN LED on a silicon substrate). Hence, a new generation of system with diversed functionalities, better energy efficiency, and smaller form factor can be achieved.

A method to integrate III-V compound semiconductors (GaN HEMT, InGaN LED, InGaAs HEMT or InGaP LED) with Si-CMOS on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily held on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. Through this method, a new generation of system with more functionality, better energy efficiency, and smaller form factor can be realized.

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems. Published version

Integration of photonic devices on silicon (Si) substrates is a key method in enabling large scale manufacturing of Si-based photonic–electronic circuits for next generation systems with high performance, small form factor, low power consumption, and low cost. Germanium (Ge) is a promising material due to its pseudo-direct bandgap and its compatibility with Si-CMOS processing. In this article, we present our recent progress on achieving high quality germanium-on-silicon (Ge/Si) materials. Subsequently, the performance of various functional devices such as photodetectors, lasers, waveguides, and sensors that are fabricated on the Ge/Si platform are discussed. Some possible future works such as the incorporation of tin (Sn) into Ge will be proposed. Finally, some applications based on a fully monolithic integrated photonic–electronic chip on an Si platform will be highlighted at the end of this article. NRF (Natl Research Foundation, S’pore) Published version

Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor. NRF (Natl Research Foundation, S’pore) Published version

The quality of germanium (Ge) epitaxial film grown directly on silicon (Si) substrate is investigated based on the electrical properties of a metal-oxide-semiconductor capacitor (MOSCAP). Different thermal cycling temperatures are used in this study to investigate the effect of temperature on the Ge film quality. Prior to high-k dielectric deposition, various surface treatments are applied on the Ge film to determine the leakage current density using scanning tunneling microscopy. The interface trap density (Dit) and leakage current obtained from the C-V and I-V measurements on the MOSCAP, as well as the threading dislocation density (TDD), show a linear relationship with the thermal cycling temperature. It is found that the Ge epitaxial film that undergoes the highest thermal cycling temperature of 825°C and surface treatment in ultraviolet ozone, followed by germanium oxynitride (GeOxNy) formation, demonstrates the lowest leakage current of ~ 2.3×10-8 A/cm2 (at -2 V), Dit ~ 3.5 × 1011 cm-2/V, and TDD

Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth. 1‐3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration. A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposureofIII-VmaterialstotheCMOSsequencewillcausetheleast disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process. Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V device structure. But the contact must also be able to withstand the temperatures of Si back-end processing steps (typically temperatures up to 500 ◦ C). Nickel silicide metallurgies, which are standard to CMOS technology, have low thermal budgets of formation and are used in more advanced CMOS processes, are explored in this work for Si-encapsulated III-V ohmic contacts. Carriertransportbetweensilicidesandsemiconductorfilmsoccurs through a tunneling mechanism requiring the silicon-encapsulation layers to be degenerately doped in order to promote tunneling. Tunneling may also occur via mid-gap interface states, which also affects thebandstructure.Inthiswork,weinvokesimilarmethodsforanalyzing our contact structures between nickel silicide and Si-encapsulated III-Vfilms. The effect of mid-gap states could be especially important in these contacts through Si-encapsulated III-V films because the lat

Here we present an initial demonstration of a dual junction step-cell using single junction (SJ) GaAs 0.76 P 0.24 cell, grown on Si 1−y Ge y /Si substrates, as the top cell and Si as the bottom cell. To demonstrate step-cell, two SJ cells are connected in series, without removing SiGe/Si carrier from III-V cell, and illuminated Si cell area is varied. Measured efficiency of optimized demo step-cell under 1 sun and without anti-reflective coating on III-V cell is ∼11.8% Using SJ cells characterization and optical data, we estimate maximum efficiency of bonded 1-μm GaAs 0.76 P 0.24 // 650-μm Si step-cell to be ∼26% at optimized total-to-top cell area ratio equal to 1.1. Results presented here show that step-cell can be used as added optimization design parameter for tandem cells.

High quality germanium (Ge), III–V (GaAs, GaN) on insulator substrates (“X”-OI, X = Ge, GaAs or GaN) are demonstrated on 200 mm Si wafer. The Ge or III–V epitaxial films are grown directly on the Si donor wafers using a metal-organic chemical vapour deposition (MOCVD). The epilayers are then bonded and transferred to another Si (001) handle wafers to form various “X”-OI substrates. The quality of the epitaxial films (in term of threading dislocations density, TDD) on the X-OI can be further improved through a thermal treatment to mid-106 /cm2.

We report the fabrication of self-aligned In 0.30 Ga 0.70 As quantum well (QW) MOSFETs on Si substrates. The layer structures for device fabrication were grown using MOCVD on a 200 mm Si substrate with threading dislocation density lower than 2×107 cm−2. Si-CMOS compatible process modules were used. The QW MOSFET achieved a drive current exceeding 200 µA/µm at V GS -V TH = 1.75 V and V DS = 1.2 V at channel length of 0.9 µm. Furthermore, peak device mobility of 3011 cm2/V·s was obtained.

We present the heterogeneous growth of InAs quantum dots (QDs) on Si platform using GaAs/Ge/Si 1− x Ge x /Si substrate. Self-assembled InAs QDs were grown on GaAs/Ge/Si 1− x Ge x /Si substrate by employing molecular beam epitaxy (MBE). The areal density, width and height of QDs were characterized using atomic force microscopy (AFM). The undulation originating from the graded Si 1− x Ge x /Si substrate causes no noticeable change in dot densities and dot dimensions across the undulated surface. The effects of V/III ratio and InAs coverage on structural properties of the QDs were investigated. The dot density increases with increasing V/III ratio and QDs with high density of 10 11 cm −2 were obtained, attributed to the reduced diffusion length of the adatoms. Lateral dimension of the QDs increases as the InAs coverage increases. The QDs coalesce at 3.0 monolayer (ML) InAs coverage. This work is beneficial to those working on III–V on Si integration.

Performance of GaInP/AlGaInP multi-quantum wells light-emitting diodes (LEDs) grown on low threading dislocation density (TDD) Germanium-on-Silicon (Ge/Si) substrates are compared and studied. Three approaches are used to realize the low TDD Ge/Si substrates. The first approach is the two-step growth of Ge/Si substrate with TDD of ∼5 ×107 cm-2. The second approach is through doped the Ge seed layer with arsenic (As) and TDD of

High-performance GaInP/AlGaInP multi-quantum well light-emitting diodes (LEDs) grown on a low threading dislocation density (TDD) germanium-on-insulator (GOI) substrate have been demonstrated. The low TDD of the GOI substrate is realized through Ge epitaxial growth, wafer bonding, and layer transfer processes on 200 mm wafers. With O2 annealing, the TDD of the GOI substrate can be reduced to ∼1.2×106 cm−2. LEDs fabricated on this GOI substrate exhibit record-high optical output power of 1.3 mW at a 670 nm peak wavelength under 280 mA current injection. This output power level is at least 2 times higher compared to other reports of similar devices on a silicon (Si) substrate without degrading the electrical performance. These results demonstrate great promise for the monolithic integration of visible-band optical sources with Si-based electronic circuitry and realization of high-density RGB (red, green, and blue) micro-LED arrays with control circuitry.

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

The integration of light emitting devices on silicon substrates ha s attracted intensive research for many years. In contrast to the InGaN light emitting diodes (LEDs) whose epitaxy technology on Si substrates is robust and mature, the epitaxy of other compound semiconductor light emitting materials covering the visible wavelength range on Si is still challenging. We have studied epitaxial growth of red InGaP light emitting materials on engineered Ge-on-Si substrates. Ge-on-Si was grown on 8’’ Si substrates in a metal organic chemical vapour deposition (MOCVD) reactor using two-step growth and cycling annealing. Threading dislocation densities (TDDs) were controlled to as low as 10 6 /cm 2 by using As-doped Ge initiation. A GaAs buffer layer and lattice-matched InGaP LEDs were grown on the Ge-on-Si sequentially in the same MOCVD process and red LEDs are demonstrated. InGaP multiple-quantum-well LED structures were grown on full 8’’ Ge -on-Si substrates and characterized. Keywords: InGaP LEDs, Ge-on-Si substrate, MOCVD epitaxy

High quality germanium(Ge)epitaxialfilm is grown directly on silicon (001) substrate with 6° off-cut using a heavily arsenic (As) dopedGe seed layer. The growth steps consists of (i) growth of a heavily As-doped Ge seed layer at low temperature (LT, at 400 °C), (ii) Gegrowth with As gradually reduced to zero at high temperature (HT, at 650 °C), (iii) pure Gegrowth at HT. This is followed by thermal cyclic annealing in hydrogen at temperature ranging from 600 to 850 °C. Analytical characterization have shown that the Geepitaxialfilm with a thickness of ∼1.5 µm experiences thermally induced tensile strain of 0.20% with a treading dislocation density (TDD) of mid 106/cm2 which is one order of magnitude lower than the control group without As doping and surface roughness of 0.37 nm. The reduction in TDD is due to the enhancement in velocity of dislocations in an As-doped Gefilm. NRF (Natl Research Foundation, S’pore) Published version

In this paper we present theoretical analysis for upper efficiency limit of a novel 2 terminal dual junction stepcell. Results show that step cell design relaxes bandgap requirements for efficient tandem cell. While conventional tandem cell with optimized bandgap combination (1.64 / 0.96 eV) has the highest efficiency (45.78 %), the step-cell design provides significant efficiency improvement for cells with non-optimized bandgap values. Efficiency upper limit for Si based step-cell with top cell bandgap equal to 1.41 eV (~ GaAs), efficiency upper limit increases from ~21% in conventional tandem cell to 38.7% for optimized step-cell design. Step-cell design provides opportunity for wider selection of materials used in tandem solar cell applications.

We have achieved the first monolithically integrated triple-junction InGaP/GaAsP/SiGe solar cell on Si substrate, achieving an adjusted efficiency of 20% AM0 1-sun. The practical achievable maximum AM0 efficiency for the optimal cell near this lattice constant is 39%. The combination of this high efficiency with the ability to process such cells on larger area lower-cost silicon substrates motivates our continued advancement of this technology. Radiation testing of 4Power cells, up to 2.7 × 1012 p+/cm2 (10MeV) show excellent radiation hardness; the novel SiGe bottom junction shows no measurable degradation after proton radiation testing, verifying such cells have application in air and space photovoltaics. Furthermore, because of the combination of high efficiency and low mass density, 4Power InGaP/GaAsP/SiGe solar cells can reach AM0 specific power approaching 1400 W/kg, greatly exceeding that of current state of the art InGaP/(In)GaAs/Ge space cells that are ∼500 W/kg. The high efficiency afforded by the unique tailoring of the multijunction bandgap cell can provide a realistic maximum of ∼500 W/m2 at AM0 1-sun.

III–V compound semiconductor HEMT integrated with silicon CMOS on a silicon common substrate is promising to open up new circuit applications and capabilities. In the conventional hybrid approach, silicon and III–V circuits are fabricated and packaged separately, and then assembled on a carrier substrate. This approach is confronted by interconnect size and losses, which affect performance, form factor, power consumption, cost, and complexity. For III/V-Si hybrid integration, direct epitaxial growth of III–V compounds on Si substrate or CMOS devices would be the most desirable approach, but the high temperature III–V materials growth would severely degrade the CMOS transistors. 3D wafer stacking combining bonding and layer transfer, on the other hand, is another promising approach to integrate III–V materials on Si substrate. In this work, 3D wafer stacking is used to integrate III–V and silicon on a common platform to realize a novel side-by-side hybrid circuit without the need for through silicon via (TSV). Integration of III–V materials (InGaAs and GaN) and SOI-CMOS on a common 200 mm Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III–V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Oxide to oxide bonding is used as a bonding medium in this case. Various oxide to oxide bonding combinations (e.g. thermal oxide bond to PECVD SiO 2 and PECVD SiO 2 bond to PECVD SiO 2 ) will be discussed and the counter-measures will be implemented. Post-bonding annealing of the bonded wafer pair is carried out at 300 °C in an atmospheric N 2 ambient for 3 hours to further enhance the bond strength to > 1200 mJ/cm2. Finally, a void free SOI-CMOS on III–V/Si hybrid structure on a common substrate can be realized after the handle wafer is released.

The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915°C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO[subscript 2] and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES., United States. Defense Advanced Research Projects Agency. COSMOS Program, United States. Office of Naval Research (Contract N00014-07-C-0629)

Monolithic CMOS compatible AlGaInP visible LED arrays have been demonstrated on a novel platform called silicon on lattice-engineered substrate (SOLES). SOLES wafers are based on Si1−xGex virtual substrate technology and are suitable for the practical fabrication of SOI CMOS circuits and III–V-based optoelectronic devices on a common silicon substrate. A combination of oxide–oxide wafer bonding and hydrogen-induced exfoliation was used to transfer a thin layer of device-quality silicon on insulator on the top of the Si1−xGex buffers graded to 100% Ge to realize SOLES. Epitaxial layers of a double heterojunction AlGaInP LED emitting near the red region of the visible spectrum (λ = 671 nm) were grown by MOCVD on SOLES wafers using a patterned oxide hard mask. CMOS compatibility was achieved by accessing the n-GaAs cathode of the LED through the underlying n-Ge layer of the Si1−xGex graded buffer rather than etching through the LED stack. The LED was capped with Si to avoid exposing CMOS tools to III–V materials during processing. The Si anode and Ge cathode of the resulting LED structure were contacted using Ti/Al CMOS compatible metallurgy. The prototype array is an important step towards the realization of monolithically integrated optical interconnects in high speed digital systems.

A range of high performance minority carrier devices have been successfully fabricated on Si virtual substrates where threading dislocation densities (TDDs) as low as 1x106 cm-2 are routinely achieved. Minority carrier lifetime data achieved on GaAs-on-Si layers exploiting this novel SiGe buffer approach to monolithic integration (τp = 10.5 ns and τn = 1.7ns) verifies the high III-V material quality. Single junction GaAs solar cells with high efficiencies for GaAs/Si of 18.1% under AM1.5-G illumination were demonstrated. Further exploiting the novel GaAs/Si material quality, even more complex minority carrier devices including dual-junction solar cells and LEDs were fabricated, yielding high performance consistent with the high III-V/Si mobilities. In both cases, certain device metrics on SiGe outperformed identical GaAs monolithic devices. Finally, a visible laser on Si was achieved, demonstrating the success and further potential of this III-V/Si integration methodology.

We have experimentally studied impact ionization (II) in the strained-Si layer of a strained-Si/SiGe heterostructure. Our key finding is that the impact ionization multiplication coefficient has a positive temperature coefficient which is opposite to that of bulk Si. Furthermore, the temperature dependence of the multiplication coefficient has been found to be exponential in nature. Our experimental work shows that the combination of a strong and positive temperature dependence of the II coefficient and the significant self-heating that this structure suffers from results in an overall impact ionization rate that is more than an order of magnitude higher than that of reference Si devices operating under identical bias conditions.

The impact of processing factors such as ion implantation and rapid thermal annealing on mobility enhancement in strained-Si n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) has been investigated. Long-channel strained-Si and bulk n-MOSFETs were fabricated with various channel-region implant doses and thermal budgets. Neutral Si and Ge species were used to study the impact of the implant damage on mobility separately from ionized impurity scattering effects. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a critical dose for a given thermal budget. Transmission electron microscopy, secondary ion mass spectrometry and Raman spectroscopy were used to investigate the mobility degradation mechanisms. Residual implant damage and implant damage enhanced Ge up-diffusion into the Si are shown to be responsible for the mobility degradation. Two-dimensional damage simulations of 30-nm scale MOSFETs are used to examine potential technological implications of these findings.

Techniques for fabricating strained Si, SiGe, and Ge on-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on-insulator. Wafer bonding with stop layers is found to be the most general approach with the ability to create ultra-thin layers of strained Si, SiGe, and Ge on-insulator with low threading dislocation densities and precise control over layer thickness.

Dual-channel heterostructures, with a tensile strained-Si layer (for electron channel) and a compressively strained-Si0.4Ge0.6 layer (for hole channel) on relaxed-Si0.7Ge0.3-on-insulator (SGOI) substrates were fabricated by bond, etch-back and epitaxial regrowth. Partially depleted p-MOSFETs were made on this strained-Si/strained-SiGe SGOI heterostructure. The hole mobility shows an enhancement of about 1.8 times at 0.2 MV cm−1, equivalent to that obtained on co-processed strained-Si/strained-SiGe p-MOSFETs fabricated on bulk relaxed Si0.7Ge0.3 virtual substrates. The limited thermal budget issue for this heterostructure is also discussed.

Although strained-silicon (e-Si) p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) demonstrate enhanced hole mobility compared to bulk Si devices, the enhancement has widely been observed to degrade at large vertical effective fields. We conjecture that the hole wave function in e-Si heterostructures spreads out over distances of ∼10 nm, even at large inversion densities, due to the strain-induced reduction of the out-of-plane effective mass. Relevant experimental and theoretical studies supporting this argument are presented. We further hypothesize that by growing layers thinner than the hole wave function itself, inversion carriers can be forced to occupy and hybridize the valence bands of different materials. In this article, we show that p-MOSFETs with thin (i.e.

Strained Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si0.7Ge0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then ...

When epitaxially growing III–V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III–V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III–V semiconductors on large size Si substrates.

A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to, Singapore. National Research Foundation (Singapore-MIT Alliance for Research and Technology)

We describe a 3D integration process flow in which the vertical distance from the CMOS layer to the novel device layer is 100–1000 nm. This short distance effectively defines the process flow as a silicon CMOS process flow and allows for the use of silicon infrastructure in process and design. Progress has been made in demonstrating various pieces of III–V device integration into a foundry 0.18 µm process on 200 mm wafers.

We demonstrated the surface functionalization of a highly three-dimensional, superhydrophilic wicking substrate using light to immobilize functional biomolecules for sensor or microarray applications. We showed here that the three-dimensional substrate was compatible with photo-attachment and the performance of functionalization was greatly improved due to both increased surface capacity and reduced substrate reflectivity. In addition, photo-attachment circumvents the problems induced by wicking effect that was typically encountered on superhydrophilic three-dimensional substrates, thus reducing the difficulty of producing miniaturized sites on such substrate. We have investigated various aspects of photo-attachment process on the nanowire substrate, including the role of different buffers, the effect of wavelength as well as how changing probe structure may affect the functionalization process. We demonstrated that substrate fabrication and functionalization can be achieved with processes compatible with microelectronics processes, hence reducing the cost of array fabrication. Such functionalization method coupled with the high capacity surface makes the substrate an ideal candidate for sensor or microarray for sensitive detection of target analytes., National University of Singapore (Graduate School for Integrative Sciences and Engineering scholarship), GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore-MIT Alliance

A novel GaAs 0.71 P 0.29 /Si tandem cell is proposed and simulated. In order to grow GaAs 0.71 P 0.29 layers on Si, Si 1−y Ge y (SiGe) buffer layers can be used but optical losses are expected. To reduce large optical losses a wafer bonded/layer transferred structure can be used that eliminates the SiGe buffer layer. In this work we propose a novel tandem step-cell design that partially exposes the underlying Si cell for both wafer bonded and SiGe based cells. We demonstrate by experiment and simulation mitigation of the optical losses associated with SiGe buffer layers. For an optimized GaAs 0.71 P 0.29 /Si tandem cell without the step cell design, simulations estimate ∼20% efficiency for the bonded structure and ∼3% for the as grown structure with a SiGe buffer. With the proposed novel step-cell design, optimum efficiency of bonded structure increases to ∼32% while for structures with SiGe the simulated efficiency reaches ∼23%. Optimum exposure of bottom cell area increases with increasing thickness and lifetime of layers above the bottom Si cell.

The effects of growth temperature, substrate offcut, and dislocation pileup formation on threading dislocation density (TDD) in compositionally graded SiGe buffers are explored. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge were grown at temperatures between 650 and 900 °C on (001)-, (001) offcut 6° towards an in-plane 〈110〉-, and (001) offcut 6° towards an in-plane 〈100〉-oriented Si substrates. The field threading dislocation density (field TDD) in the on-axis samples varied exponentially with temperature, from 3.7×106 cm−2 at 650 °C to 9.3×104 cm−2 at 900 °C. The activation energy for dislocation glide in this series, calculated from the evolution of field TDD with growth temperature, was 1.38 eV, much lower than the expected value for this composition. This deviation indicates that strain accumulating during the grading process at low growth temperatures is forcing further dislocation nucleation, resulting in a deviation from pure glide-limited relaxation. The TDD of samples grown on offcut substrates exhibited a more complicated temperature dependence, likely because films grown on offcut substrates have an increased tendency towards saturation in dislocation reduction reactions at high temperature. Dislocation reduction processes were further explored by initiating compositional grading up to 15% Ge at 650 °C and continuing the grade to 30% Ge at 900 °C. The low temperature portion of this growth provided an excess concentration of threading dislocations which could subsequently be annihilated during the high temperature portion of the growth, enabling a comparison of reduction rates for different substrate offcuts. Combining these results with threading dislocation densities in a variety of other samples, a complete picture of strain relaxation kinetics in compositionally graded SiGe/Si emerges. Generally, strain relaxation in these structures is limited by dislocation glide, and threading dislocation densities are independent of final Ge content. However, we theorize that dislocation pileup formation inhibits the strain relaxation process and is therefore accompanied by a rise in field threading dislocation density. Based on these results, we now have a predictive model for TDD in compositionally graded SiGe/Si over a wide range of growth conditions.

Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

A scalable method to fabricate germanium on insulator (GOI) substrate through epitaxy, bonding, and layer transfer is reported. The germanium (Ge) epitaxial film is grown directly on a silicon (Si) (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) wafer to form the GOI substrate. The Ge epilayer on GOI substrate has higher tensile strain (from 0.20% to 0.35%) and rougher surface (2.28 times rougher) compared to the Ge epilayer before transferring (i.e., Ge on Si wafer). This is because the misfit dislocations which are initially hidden along the Ge/Si interface are now flipped over and exposed on the top surface. These misfit dislocations can be removed by either chemical mechanical polishing or annealing. As a result, the Ge epilayer with low threading dislocations density level and surface roughness could be realized. Published version

Annealing effects on hole and electron mobility in dual-channel structures consisting of strained Si and Si1−yGey on relaxed Si1−xGex layers (x=0.3/y=0.6, and x=0.5/y=0.8) were studied. Hole mobility decreases sharply, but electron mobility is quite immune to annealing conditions of 800 °C, 30 min or 900 °C, 15 s. The hole mobility decrease is more severe in dual-channel structures with higher Ge contents. Hole mobility degradation is a direct result of Ge outdiffusion from the Si1−yGey layer, and the resulting decreased Ge content. Ge diffusion preferentially towards the Si1−xGex buffer layer, rather than the Si cap layer, is a reason that electron mobility is highly immune to such annealing.

Ultra-high vacuum scanning tunneling microscopy and depth profiling X-ray photoelectron spectroscopy were used to evaluate two methods for cleaning Si 1− x Ge x (001) films using ex-situ surface oxidation followed by in-situ oxide desorption at temperatures ≤ 1025°C. Dry ultra-violet ozone cleaning was found to be fast, simple, and highly effective for cleaning Si 1− x Ge x (001) surfaces with a wide range of Ge content as well as standard Si(001) surfaces, consistently yielding lower surface particulate densities than a standard wet chemical cleaning technique.

We describe the research results produced from our focus on integrating GaN HEMTs and LEDs into silicon CMOS integrated circuits. Although current component markets are driving most GaN HEMT development, we have undertaken an innovation path in which the value of an integrated GaN device in a silicon design environment is the driver for materials and device development. Specifically, our integrated process flow involving foundry production of front and back end standard CMOS processes demands certain GaN epitaxial and material constraints that are different than constraints on non-integrated devices. We report on 200 mm GaN-on-Si 725 um thick engineered substrates formed through a combination of MOCVD and wafer bonding processes. Our optimized 200 mm GaN-on-Si (111) epitaxial wafers have bow values < 30 um, with total III-N film thicknesses of 2.7 um including a 1.5 um capping GaN layer. XRD FWHM values of 400 and 380 arcsec for (002) and (102) reflections indicate TDD of approximately 4e8 cm-2. CMOS-compatible GaN HEMTs demonstrated on these wafers have achieved 2DEG mobilities of ~1200 cm2/Vs and sheet carrier densities of 1-2e13 cm-2, with Id, max values of 700 mA/mm and 25 GHz fT, fmax for Lg = 0.25 um. High quality InGaN/GaN MQW LEDs emitting at 450 nm with total III-N stack thickness of 3.7 um have also been demonstrated. Central emission wavelength standard deviation of < 2 nm was achieved across the entire 200 mm, wafer, and typical devices exhibited turn-on at ~2.5 V with diode ideality factor of 2.8. We have developed wafer engineering techniques such as edge encapsulation and substrate replacement to address wafer fragility issues typically associated with GaN on SEMI-spec 725 um Si wafers. This also leads new wafer/device platforms such as GaN-OI and CMOS + GaN that will open new avenues in device performance and integration of III-N with Si CMOS.

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm−2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with IDS of 70 μA/μm and gm of above 60 μS/μm, demonstrating the high quality of the grown materials.

The capture kinetics and trapping properties of a dislocation related electron trap detected in strain‐relaxed, compositionally graded Ge0.3Si0.7/Si grown by rapid thermal chemical‐vapor deposition are investigated by deep‐level transient spectroscopy (DLTS). The volume DLTS trap concentration scales linearly with the areal threading dislocation density, as determined by electron‐beam‐induced current measurements on samples with different compositional grading rates, indicating that the detected trap is most likely associated with dislocation core states in these graded structures. The dislocation related trap exhibits both the logarithmic dependence of DLTS peak height on fill pulse time tp, and broadened DLTS peaks which typically characterize carrier trapping at dislocations. These effects are quantified and analyzed to gain insight into the trapping properties of dislocations in GeSi/Si heterostructures and to investigate the effects of dislocation related carrier trapping on DLTS measurements. It is ...