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Nanoscale structures have been recently proposed as charge storage nodes due to their potential applications for future nanoscale memory devices. Our approach is based on the idea of using Si nanodots as discrete floating gates. To experimentally investigate such potential, we have fabricated MOS structures with Si nanocrystals. The dots have been deposited onto an ultra-thin tunnel oxide by chemical vapor deposition (CVD) of SiH4, and then annealed at 1000 degreesC for 40 s, to crystallize all the dots. After deposition, the dots have been covered by a CVD SiO2 layer, thus resulting completely embedded into stoichiometric silicon oxide. The nanocrystal density and size have been studied by energy filtered TEM (EFTEM) analysis. An electrostatic force microscope has been used to locally inject and image charge. By applying a relatively large tip voltage and reducing the tip to sample separation down to the contact with the surface sample, a few dots have been charged, by appearing as protrusions on the surface. The charged dots have been monitored for up to 30 min, by showing no discharge effects either vertically, through the double barrier of oxide layers, or laterally, via cross talk effect between other close dots.

Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness. © 2002 Elsevier Science B.V. All rights reserved.

We report on the improvement of short circuit current (JSC), fill factor (FF), and open circuit resistance (ROC) in hydrogenated amorphous silicon (a-Si:H) photovoltaic cells with a p-type/intrinsic/n-type structure, achieved by the addition of an ultra-thin molybdenum film between the p-type film and the transparent conductive oxide/glass substrate. For suitable conditions, improvements of ≈10% in average internal quantum efficiency and up to 5%–10% under standard illumination in JSC, FF, and ROC are observed. These are attributed to the excitation of surface plasmon polariton modes of the a-Si:H/Mo interface.

The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh time compared to conventional dynamic random access memory cells. © 2002 American Institute of Physics.

In this paper we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, Silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials. ©2004 IEEE.

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cells for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.

Structural properties of silicon rich oxide films (SRO) have been investigated by means of micro-Raman spectroscopy and transmission electron microscopy (TEM). The layers were deposited by plasma enhanced chemical vapor deposition using different SiH4/O2 gas mixtures. The Raman spectra of the as-deposited SRO films are dominated by a broad band in the region 400-500 cm-1 typical of a highly disordered silicon network. After annealing at temperatures above 1000°C in N2, the formation of silicon nanocrystals is observed both in the Raman spectra and in the TEM images. However, most of the precipitated silicon does not crystallize and assumes an amorphous microstructure. © 2002 The Electrochemical Society. All rights reserved.

We have realized nanocrystal memories by using silicon quantum dots embedded in silicon dioxide. The Si dots with the size of few nanometers have been obtained by chemical vapor deposition on very thin tunnel oxides and subsequently coated with a deposited SiO2 control dielectric. A range of temperatures in which we can adequately control a nucleation process, that gives rise to nanocrystal densities of ∼3×1011 cm−2 with good uniformity on the wafer, has been defined. The memory effects are observed in metal-oxide-semiconductor capacitors or field effect transistors by significant and reversible flat band or threshold voltage shifts between written and erased states that can be achieved by applying gate voltages as low as 5 V. The program-erase window does not exhibit any change after 105 cycles on large area cells showing that the endurance of such a memory device which uses a thinner tunnel oxide is potentially much higher than that of standard nonvolatile memories. Moreover, good retention results are ...

Metal-oxide-semiconductor capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers are presented and investigated by transmission electron microscopy and electrical measurements. The grain size distribution and the amount of crystallized silicon remaining in SRO after annealing have been studied by transmission electron microscopy, whereas the charge trapping and the charge transport through the dots in the SRO layer have been extensively investigated by electrical measurements. Furthermore, a model, which explains the electrical behavior of such SRO capacitors, is presented and discussed. © 2001 American Institute of Physics.

To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials wereannealed in N2 ambient at temperatures between 950 and 1100 °C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory function of such structures has been investigated in metal-oxidesemiconductor (MOS) capacitors with a SRO film sandwiched between two thin SiO2 layers as insulator and with an n+ polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance-voltage characteristics and they have been studied as a function of bias.

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

By electrical measurements we investigate the charge trapping and the charge transport in MOS capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers.