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An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed. [ABSTRACT FROM AUTHOR]

Au/CaF2/nSi(111) structures with 4–5 monolayers of epitaxial fluoride are fabricated and electrically tested. The leakage current in these structures was substantially smaller than in similar samples reported previously. Simulations adopting a Franz-type dispersion relation with Franz mass of mF∼1.2m0 for carriers in the forbidden band of CaF2 reproduced the measured current-voltage curves quite satisfactorily. Roughly, these curves could also be reproduced using the parabolic dispersion law with the electron mass of me=1.0m0, which is a material constant rather than a fitting parameter. Experimental facts and their comparison to modeling results allow qualification of the crystalline quality of fabricated structures as sufficient for device applications. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon-hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices. [ABSTRACT FROM AUTHOR]

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]

Stress-induced enhancement of electron mobility has primarily been attributed to the splitting of the conduction band minima. However, experiments have indicated that the mobility enhancement cannot solely be attributed to this effect, and a recent study has shown that stress along the lang110rang direction leads to a change of the effective mass. This work investigates the effect of the variation of the effective mass with stress along the lang110rang direction on the electron mobility. An improved low-field mobility model incorporating the effective mass change is presented [ABSTRACT FROM PUBLISHER]

We present results of fully two-dimensional numerical simulations of silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) in comparison with experimental data. Among the critical modeling issues discussed in the paper, special attention is focused on the description of the anisotropic majority/minority electron mobility in strained SiGe grown in Si. [Copyright &y& Elsevier]

Abstract: The negative bias temperature instability (NBTI) of nanoscaled Si0.45Ge0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (ΔV th) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average ΔV th step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed. [Copyright &y& Elsevier]

We present a direct approach to obtain scattering parameters (S-parameters) and other derived figures of merit of SiGe-HBTs by means of small-signal (ac) analysis. Therefore, an additional simulation mode has been implemented in the three-dimensional device simulator Minimos-NT. Several additional features are provided for efficiently obtaining various small-signal parameters. The accuracy of the results is proven by analytical methods and by comparison with measurements. [Copyright &y& Elsevier]