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GaN capped Al0.2Ga0.8N/AlN/GaN heterostructures were grown on 3C-SiC (111)/Si (111) substrates and used for the implementation of digital circuits. The AlGaN/GaN heterostructure was grown by MOCVD, whereas the 3C-SiC(111)/Si(111) pseudosubstrate was fabricated using low temperature LPCVD. The SiC layer was 50 nm thick. The presented digital circuits were realised using depletion-mode load and drive high electron mobility transistors. In order to demonstrate the feasibility of digital circuits using standard depletion mode device technology, NAND and NOR digital circuits were designed and fabricated using a standard Au/Ti/Al/Ti and Au/Ni metallisation scheme for the ohmic and Schottky contacts of the high electron mobility transistors, respectively. The logic function and the voltage transfer characteristics of the fabricated logic circuits are demonstrated and analysed. [ABSTRACT FROM AUTHOR]

The realization of depletion-mode planar and both enhancement- and depletion-mode tri-gate high electron mobility transistors (HEMTs) based on Al0.2Ga0.8N/AlN/GaN heterostructures grown on silicon substrates using an ultrathin 3C-SiC transition layer is presented. This substrate configuration simplifies heterostructure growth compared to SiC and thick 3C-SiC substrates. The threshold voltage of the tri-gate devices strongly depends on the AlGaN/GaN body (fin) width. A transition from depletion-mode to enhancement-mode operation occurred at 110 nm body width for tri-gate devices without Si3N4 passivation, and is expected to occur at 75 nm for devices with Si3N4 passivation. Threshold voltages of −0.25/0.35 V were achieved at fin widths of 82/100 nm with/without Si3N4 passivation, respectively, for the tri-gate HEMTs in comparison to −3.5 V for the planar HEMTs. Cutoff frequencies fT of 45 GHz and maximum frequencies of oscillation fmax of 50 GHz have been measured for our best 100-nm tri-gate enhancement-mode HEMTs, while depletion-mode planar HEMTs with the same gate length showed 110 GHz for both fT and fmax. This demonstrates the applicability of the developed substrate configuration for high-performance device applications. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of an automated roll-to-roll fluidic self-assembly system based on the surface tension driven self-assembly with applications in the field of macroelectronics. The reported system incorporates automated agitation, web motion, component dispensing, and recycling. The process enables the assembly and electrical connection of semiconductor dies/chips in a continuous and parallel fashion over wide area substrates. At present, the method achieves an assembly rate of 15 000 chips per hour and an assembly yield exceeding 99%, testing assembly of standard square-shaped dies, 300–1000 \mu \textm size. Scaling the system to any desired throughput is possible due to the parallel manner of self-assembly. The identification and the modeling of the relationship between process parameters and forces have been studied and experimentally verified by testing the effect of the web angle, agitation on assembly, and detachment rates. As an application, we demonstrate the realization of a solid-state lighting module. This particular application requires the assembly of a conductive multilayer sandwich structure, which is achieved by combining the introduced assembly process with a novel lamination step. [2015-0105] [ABSTRACT FROM AUTHOR]