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The strongly correlated thermoelectric properties have been a major hurdle for high-performance thermoelectric energy conversion. One possible approach to avoid such correlation is to suppress phonon transport by scattering at the surface of confined nanowire structures. However, phonon characteristic lengths are broad in crystalline solids, which makes nanowires insufficient to fully suppress heat transport. Here, we employed Si-Ge alloy as well as nanowire structures to maximize the depletion of heat-carrying phonons. This results in a thermal conductivity as low as ∼1.2 W/m-K at 450 K, showing a large thermoelectric figure-of-merit (ZT) of ∼0.46 compared with those of SiGe bulks and even ZT over 2 at 800 K theoretically. All thermoelectric properties were "simultaneously" measured from the same nanowires to facilitate accurate ZT measurements. The surface-boundary scattering is prominent when the nanowire diameter is over ∼100 nm, whereas alloying plays a more important role in suppressing phonon transport for smaller ones.

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~1010. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe2 p−n homojunction. The WSe2 FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe2 FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%. [ABSTRACT FROM AUTHOR]

In this paper, a novel on-interposer passive equalizer is proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the on-interposer shunt metal lines to produce the high-pass filter. This filter enables the proposed equalizer to exhibit wideband channel equalization and low power-consumption. Based on the equivalent-circuit model of the proposed on-interposer passive equalizer, the physical dimensions of the equalizer are optimized for 30-Gb/s serial data transmission. The performance of the proposed equalizer with the optimized dimensions was successfully demonstrated by both frequency- and time-domain measurements at data rates of up to 30 Gb/s. In addition, a compact on-interposer passive equalizer was designed for the wide I/O interposer using the same mechanism. The improved quality of serial data transmission in the equalized wide I/O on-interposer channel was successfully verified by simulations at data rates of up to 10 Gb/s. [ABSTRACT FROM AUTHOR]

An analytic scalable model of a differential signal through-silicon via (TSV) is proposed. This TSV is a ground-signal-signal-ground (GSSG)-type differential signal TSV. Each proposed analytical equation in the model is a function of the structural and material design parameters of the TSV and the bump, which is scalable. The proposed model is successfully validated with measurements up to 20 GHz for the fabricated test vehicles. Additionally, the scalability of the proposed model is verified with simulations by using Ansoft HFSS to vary the design parameters, such as the TSV diameter, pitch between TSVs, and TSV oxide thickness. On the basis of the proposed scalable model, the electrical behaviors of the GSSG-type differential signal TSV are analyzed with respect to the design variations in the frequency domain. Additionally, the electrical performances of a GSSG-type differential signal TSV are evaluated and compared to that of a ground-signal-ground-type single-ended signal TSV, such as insertion loss, characteristic impedance, voltage/timing margin, and noise immunity. [ABSTRACT FROM PUBLISHER]

In this paper, we propose models for large-sized silicon interposer power distribution networks (PDNs) and through silicon via (TSV)-based stacked grid-type PDNs using a segmentation method. We model the PDNs as distributed scalable resistance (R), inductance (L), conductance (G), and capacitance (C)-lumped models for an accurate estimation of the PDN impedance, including PDN inductance and wave phenomena such as the mode resonance at the high end of the frequency range. For this estimation, it is necessary to accurately model all transmission line (TL) sections that form the PDNs using a conformal mapping method and a phenomenological loss equivalence method (PEM). After modeling the individual TL sections, all the TL sections are connected based on a segmentation method, which is a matrix calculation method. The segmentation method accelerates the calculation speed for the PDN impedance estimation. The proposed models are successfully validated by simulations and measurements in the frequency range 0.1–20 GHz. Using the proposed models, we estimate and analyze the impedance curves of the interposer PDN and TSV-based stacked grid-type PDN with respect to the variations in the horizontal area of the interposer PDN and the number of power/ground TSVs in TSV-based stacked grid-type PDNs, respectively. [ABSTRACT FROM PUBLISHER]

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements. [ABSTRACT FROM AUTHOR]

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases. [ABSTRACT FROM PUBLISHER]

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided - 17∼dB and - 10∼dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively. [ABSTRACT FROM AUTHOR]

Abstract: Thermal properties of the AlGaN/GaN Schottky barrier diodes were investigated, using a pulsed-IV measurement technique. The thermally degraded mobility in the DC-bias configuration was restored, when the pulse-bias voltages were applied. It was observed that heat generation was minimized, using a pulse width of 500 ns and pulse period of 10 ms. For the SBDs consisting of 5 μm of anode–cathode distance, on-resistance measured by the pulse-IV and DC-IV were 1.6 and 6.2 Ω-mm, respectively. We also demonstrated the device-width dependence of the thermal properties of the SBDs. We found that the performance of the power devices can be greatly influenced by the heat generation. [Copyright &y& Elsevier]