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In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (tSi) ranging from 15 nm to 2 nm on device performance and reliability. Thinning tSi from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (VTH) and subthreshold swing (SS). However, further reduction of tSi to 5 nm, while continuing to decrease SS, caused an increase in VTH due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing tSi to 2 nm resulted in an increase in both SS and VTH mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning tSi enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of tSi in terms of the degradation of VTH, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of tSi is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal tSi range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design. [ABSTRACT FROM AUTHOR]

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (${G}_{m\_{}{\text {max}}}$) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (${V}_{\text {BG}}$) operation mode, the ${V}_{\text {BG}}$ can provide a wide threshold voltage (${V}_{\text {TH}}$) tuning range ~2 V when the ${V}_{\text {BG}}$ is modulated from 0 to −4 V. The negative ${V}_{\text {BG}}$ bias stress would induce electron injection from the BG, resulting in positive ${V}_{\text {TH}}$ shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative ${V}_{\text {BG}}$ stress, using ${V}_{\text {BG}}$ to modulate the ${V}_{\text {TH}}$ of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent ${V}_{\text {BG}}$ to adjust the ${V}_{\text {TH}}$ of the JL-TFTs to meet the multiple- ${V}_{\text {TH}}$ requirement of advanced integrated circuits. [ABSTRACT FROM AUTHOR]

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ($V_{\mathrm {TH}}$) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ($I_{\mathrm {ON}}$) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$. The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT. [ABSTRACT FROM AUTHOR]

Hot-carrier stress (HCS) characteristics of polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors are investigated and compared with the conventional poly-Si thin-film transistors (TFTs). After HCS with VDS = 2VGS = 20 V for 1000 s, poly-Si TFT exhibits significant ON-state current (Ion) degradation ~85% and two-step subthreshold swing (SS) behavior due to the serious lattice damage between the pinch-off point and the drain. For the poly-Si tunnel field-effect transistor (TFET), less Ion degradation ~70% is observed. In addition, the stress drain voltage (VDS) effect of the HCS is also studied. When the stress VDS is increased from 10 to 15 V, the poly-Si TFETs exhibit more obvious stressed Ion degradation (~24.4%) than that of poly-Si TFTs (~6.5%). When the stress VDS is further increased from 15 to 20 V, the poly-Si TFETs exhibit less stressed Ion degradation (~62.4%) than that of poly-Si TFTs (~85%). Because the increase in the stress drain voltage is dropped in the pinch-off region of the poly-Si TFETs after the pinch-off phenomenon occurs, resulting in less impact on the stress field at the tunnel junction. When the channel length is decreased, the results show that the HCS effect of poly-Si TFETs is insensitive to the channel length, and the poly-Si TFTs show more serious electrical degradation and breakdown behavior with the scaling down of the channel length. The stronger HCS immunity of poly-Si TFETs would be an important advantage to replacing poly-Si TFTs for applications of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing (SS) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS. Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor. [ABSTRACT FROM AUTHOR]

We demonstrate the polycrystalline-silicon (poly-Si) junctionless (JL) thin-film transistor (TFT) with a planar structure and an ultra-thin channel film thickness ~1.5-nm exhibiting subthreshold swing (S.S.) less than 60 mV/decade. The S.S. of the poly-Si JL-TFT shows abnormal drain-voltage dependence, which the higher drain voltage leads to the smaller S.S. The minimum S.S. (S.S.min) observed in this letter is about 30 mV/decade, which is a record low S.S.min. The sub-60-mV/decade S.S. of the poly-Si JL-TFT is attributed to the impact ionization effect resulting from the high lateral electric field at the drain side at OFF-state. It is different from the conventional inversion-mode transistor, whose pinch-off point is observed at ON-state rather than the OFF-state. The lateral electric field is also found to be increasing with decreasing the channel thickness, and as a consequence, the impact ionization effect is more pronounced when the channel thickness is thinner. This letter shows a new concept for JL transistors, which would be helpful for the development of poly-Si JL-TFTs and the applications of 3-D integrated circuit and non-volatile memory. [ABSTRACT FROM AUTHOR]

In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH 3 ) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (N GB ) of poly-Si channel film and the interface trap state densities (N it ) at the gate-oxide/poly-Si interface. About 27% reduction of N GB by NH 3 plasma surface treatment can reduce the minimum drain current ~ 0.51 × and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of N it by NH 3 plasma surface treatment can significantly enhance the on-state current ~ 2.86 × due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly-Si tunnel-TFTs by the NH 3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility \muFE, rising from 14.33 to 22.33 \cm^2/\break\V\cdot \s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility \muFE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified. [ABSTRACT FROM AUTHOR]

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (Nit) and bulk traps (NGB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit \sim 4.5\times higher ON-state current I_{\text {ON}} , subthreshold swing reduction \Delta \text{S}$ .S. \sim 202$ mV/decade, and larger \sim 7.2\times $ ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced and a reduced \text{N}_{\mathrm {\mathbf {GB}}}\sim 0.36 \times , respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics. [ABSTRACT FROM PUBLISHER]

In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is \10^-7 A by the band-to-band tunneling current. A much larger memory window (>\12 \ \V) and good data retention time (>\10^8\ \s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications. [ABSTRACT FROM PUBLISHER]