Search

In this paper, for the first time, the performance of a Ge p-channel FinFET in the presence of random grain-orientation-induced gate-metal work function variability (WFV) is reported. The statistical fluctuation in threshold voltage ( VT ) and subthreshold swing (SS) are estimated for a Ge p-FinFET of varying channel length, fin width, equivalent oxide thickness of the gate dielectric, and supply voltage using a 3-D numerical device simulator, and compared with that for a similarly sized Si p-FinFET. The results indicate that the Ge FinFET shows better immunity to WFV-induced VT fluctuations, whereas a higher variation in SS is observed for such devices as compared with its Si counterpart. [ABSTRACT FROM PUBLISHER]

In this letter, the random discrete dopant (RDD) induced variability for a Ge junctionless (JL) p-FinFET is reported. A one-to-one comparison of the RDD-induced variability between Ge and Si JL FinFETs for varying device parameters and supply voltage is made using a 3-D numerical device simulator. Results indicate that the Ge JL FinFET shows higher immunity to RDD induced threshold voltage fluctuation than its Si counterpart, which is partially due to the higher dielectric constant of Ge than Si. Because of the lower band gap of Ge than Si, a higher variation in subthreshold swing due to RDD is, however, observed for Ge devices. Technology scaling is found to reduce σSS, although it has almost no effects on σVT for both types of devices. The difference in sSS between Ge and Si devices decreases with technology scaling, which makes Ge very attractive for scaled p-type JL FinFETs. [ABSTRACT FROM AUTHOR]

We propose a novel hybrid CMOS comprising a Si-channel pMOSFET and an asymmetric InP/InGaAs nMOSFET in the nanometer regime for analog applications. The performance of such a CMOS is evaluated in terms of voltage gain and gain-bandwidth (GBW) product at two different channel lengths ( Lg ), 50 and 30 nm, using extensive device simulations. Our investigations reveal that the maximum gain of the hybrid CMOS inverter is improved by 37.5% and 92.1% for asymmetric In0.75Ga0.25As nMOS devices with InP drain at Lg = 30 nm for W\!p/Wn = 3 and 8, respectively, as compared with an equally sized Si inverter having W\!p/Wn = 3 . In addition, GBW product of hybrid CMOS (HAS3) comprising asymmetric In0.75Ga0.25As nMOSFET with InP source and Si pMOSFET is increased by 148.1% and 260.4% at Lg = 30 and 50 nm, respectively, for Wp/Wn = 3 , compared with its Si counterpart. Furthermore, the HAS3 device yields the highest GBW peak, unity current gain frequency, and maximum oscillation frequency as compared with other hybrid and Si CMOS devices at Lg=30 and 50 nm. [ABSTRACT FROM AUTHOR]

CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25 As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for Dit exceeding 5 × 1012eV−1 · cm−2. [ABSTRACT FROM PUBLISHER]

A tunnel field-effect transistor (FET) (TFET), in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub-0.6-V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer–drain overlap on the device characteristics of such silicon TFET is reported in this paper. It is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer–drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel-resistance limited region results in long-channel metal–oxide–semiconductor FET-like output characteristics for such a structure. Short-channel effects, such as drain-induced barrier lowering, are also greatly suppressed in it. Results of the investigation on the scaling properties of such devices are also reported. [ABSTRACT FROM AUTHOR]

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-mV/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal–oxide–semiconductor field-effect transistor, particularly for low-power applications. It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not. A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time. It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used. A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages. [ABSTRACT FROM AUTHOR]

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low-\kappa dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (\sim30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate–source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high-\kappa spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it. [ABSTRACT FROM PUBLISHER]

MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance (gm), transconductance-to-drain-current ratio (gm/ID), drain resistance (RO), intrinsic gain, and unity-gain cutoff frequency (fT) are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications. [ABSTRACT FROM AUTHOR]

We investigate the logic performance of hybrid (H) CMOS devices comprising Ge p-MOSFETs and Si n-MOSFETs in terms of rise time, fall time, propagation delay and noise margins using extensive numerical device simulation. We analyse CMOS devices featuring channel thickness (T ch ) ranging 5–10 nm, spacer length (L sp ) from 1 to 10 nm at channel length (L g ) of both 20 and 30 nm. Our investigation reveals that hybrid CMOS inverters exhibit reduction in rise time and propagation delay by 53.5% and 31.6% as compared with the corresponding Si value, respectively for the ratio of widths of p- and n-MOSFETs (r) = 3, T ch = 7 nm and L sp = 5 nm at L g = 20 nm. Furthermore, the frequency of oscillations of a 3-stage ring oscillator constructed with hybrid CMOSFETs shows a significant improvement of 151.7% at L g = 20 nm for r = 1, over its equivalent Si counterpart. [ABSTRACT FROM AUTHOR]