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In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low- $k$ spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view. [ABSTRACT FROM AUTHOR]

We report the modeling and simulation of the soft-error rate (SER) in CMOS 130 nm SRAM induced by alpha-particle emission in silicon due to uranium contamination at ppb concentration levels. Monte-Carlo simulation results have been confronted to experimental data obtained from long-duration (>20\ 000 h) real-time measurements performed at the under-ground laboratory of Modane (LSM) and from experimental counting characterization using an ultra low background alpha-particle gas proportional counter. The calibration of simulations with the measured SER allowed us to determine a ^238U contamination level of 0.37 ppb (considered at secular equilibrium) in very good agreement with both corresponding alpha-particle emissivity levels measured and simulated at wafer-level in the range 1.1 to 2.3 \times 10^-3 alpha/cm^2/h. [ABSTRACT FROM AUTHOR]

A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z 2 -FET memory cell features a large current sense margin and small OFF-state current at 25 °C and 85 °C. Moreover, low power consumption during state ‘1’ writing is achieved with ~ 0.5 V programming voltage. These specifications make the Z 2 -FET an outstanding candidate for low-power eDRAM applications. [ABSTRACT FROM AUTHOR]