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This paper reviews the different stressor techniques used in microelectronics, in the scope of the Ultra-Thin Body & Buried Oxide Fully-Depleted Silicon On Insulator technology (UTBB FD-SOI). We compare the mechanical efficiency of the various stressors and present the impact of device dimensions (active area, gate length and pitch) on their efficiency. Our study emphasizes the high efficiency, for the FD-SOI technology, of the intrinsically strained channels, compared to the traditional embedded raised source/drain and contact-etch stop liner. With these techniques FD-SOI technology has already demonstrated channel stress higher than 1.5 GPa for n type transistor and −2.3 GPa for the p type devices and we envision channel stress values up to ±3 GPa for n and p transistor channel, respectively. This performance is partly due to the mechanical configuration of intrinsically strained channels, in parallel mode rather than in serial mode as for the previous generation of stressors, which makes them less sensitive to the scaling of the contacted gate pitch. We also highlight another key element the high mechanical stability of the UTBB technology, related to the limited channel thickness (around 6 nm) which enables achieving highly stressed channel without substantial adaptation of the integration flows. [ABSTRACT FROM AUTHOR]

Abstract: Local stressors techniques are extensively used in CMOS technologies starting with the 90nm node to compensate the mobility loss induced by extensive scale down. The purpose is to generate some strain within the silicon channel to enhance carrier mobility. To achieve nMOS performance at the 45nm node, gate stressors are required in addition to standard nitride liners. With this option, the stress generated within the gate is directly transmitted into the channel and more than 10% gain in saturation current is achievable on nMOS. Stress is generated within the polysilicon gate through annealing under a capping liner. After liner removal, a part of this stress is memorized within the gate material. Final gate stress depends on both polysilicon pre-treatments and liner properties. This paper deals with material studies performed on capping liners in parallel to tests on electrical devices. Important parameters to generate stress under capping are presented. This allows providing a simple model and guidelines for further optimization. [Copyright &y& Elsevier]

Abstract: In the framework of the development of strained channel materials, the mechanical stress induced in silicon by a silicon nitride stressor layer is studied. The investigated samples are sub-micrometric periodic arrays of polysilicon lines deposited on thermally oxidised single crystal (001) Si substrate and capped with silicon nitride. We compare the stress induced in the silicon substrate by three layouts: without Si3N4, with a tensile Si3N4 or with a compressive Si3N4 layer on top of the poly lines. The periodic strain field in silicon is investigated by high resolution X-ray diffraction which is very sensitive to local strain (<10−4) and is non-destructive. The lines array induces a periodic strain field in silicon, which gives rise to distinct satellites in reciprocal space. The intensity of these satellites is related to the strain field in one cell. X-ray reciprocal space maps are measured on a 4 circles goniometer with a laboratory source. First experimental mappings around the symmetrical 004 Si Bragg peak are presented here. Elastic calculations are performed with a Finite Element Modelling code in order to extract the displacement field that is useful for structure factor calculations within kinematical approximation. The calculations are necessary for explaining the experimental reciprocal space maps intensity envelope and comparing the strain induced by the three investigated layouts. [Copyright &y& Elsevier]