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A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices. [ABSTRACT FROM AUTHOR]

Recent advances demonstrated the feasibility of realizing spin-based quantum computation in Silicon. To make further progress towards a large-scale implementation of spin-based quantum device technologies, a reliable fabrication process with good yield and device uniformity is a crucial requirement. We address this challenge by integrating a prototype spin qubit device in a 300 mm process, using state-of-the-art, CMOS-compatible process steps. We demonstrate well-formed single-electron transistors with a feature size of 50 nm, individual electron controllability and show multi-gate control uniformity from room-down to low-temperature. Dots with charging energies of 1–2 meV and sizes of around 46 nm are estimated, in excellent agreement with design geometry. The noise power spectrum reveals 1/f noise with an amplitude of $2~\mu $ eV at 1 Hz. This successful integration enables further exploration of reproducible Silicon-based spin qubit devices and opens paths for systematic investigation of the performance and scalability of future spin-based qubit devices. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

We propose a novel metal/silicon/metal (MSM) selector using ultrathin (<10~nm) undoped amorphous silicon (a-Si) for resistive-RAM selector application. The new selector behaves as a bidirectional diode, showing a high current drive (\sim2.2~MA/cm)^2, high selectivity (\sim240 for 1/2 bias), fast switching speed (<1~ns), and excellent endurance (>10^8~cycles at target drive current). The doping-free a-Si structure alleviates the dopant-induced variability concerns for ultrascaled devices and eliminates the need for a dopant-activation anneal. Circuit simulations show feasibility of 1-Mb array, with over 25% read margin and 70% write margin, when using the new MSM structure as a selector for a HfO2-based resistive switching memory element. [ABSTRACT FROM AUTHOR]

Abstract: We report the large area growth of highly conductive carbon nanosheets (CNS) composed of few layer graphene on 200mm diameter Si substrates using conventional radio frequency plasma-enhanced chemical vapour deposition. Raman spectroscopy is used to characterise the evolution of the CNS nucleation and growth with time in conjunction with TEM revealing the nano-sized graphene-like nature of these films and the intimate contact to the substrate. An individual sheet can have edges as thin as 3 graphene layers. The influence of the growth support layer is also discussed as film growth is compared on titanium nitride (TiN) and directly on Si. Electrochemical cyclic voltammogram (CV) measurements reveal these layers to form an excellent electrical contact to the underlying substrate with excellent stability towards oxidation whilst having a large electrochemical surface area. The resistance of a 150nm film was measured to be as low as 20μohmcm. The high percentage of narrow few layer graphene edge sites exposed allows for faster electrochemical reaction rates compared to carbon nanotubes (CNTs) and other electrode materials (glassy carbon and Pt). [Copyright &y& Elsevier]