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This paper presents a lumped scalable model for spiral inductors in a radio frequency (RF) gallium nitride (GaN) technology on silicon substrate. The model has been developed by exploiting electromagnetic (EM) simulations of geometrically scaled spiral inductors. To this aim, the technology substrate, i.e., the metal back-end-of-line along with dielectric and semiconductor layers of the adopted GaN process, has been validated by means of experimental data and then used to define the EM simulator set-up for the spiral inductors. The proposed model adopts a simple π-topology with only seven lumped components and predicts inductor performance in terms of inductance, quality factor (Q-factor) and self-resonance frequency (SRF) for a large range of geometrical parameters of the spiral (i.e., number of turns, metal width, inner diameter). [ABSTRACT FROM AUTHOR]

This brief demonstrates a fully contactless wafer-level testing based on UHF radio identification (RFID) technology enriched by high-quality on-chip antenna. The antenna, which uses exactly the same tag IC area (i.e., 0.45 mm2), exploits a low-cost post-process consisting of a thick dielectric layer and a copper metal, thus significantly improving the quality factor with respect to a standard CMOS implementation. Contactless wafer-level testing of a tag array is performed by simultaneous inductive coupling with a customized near-field reader. With a 27-dBm standard UHF RFID reader, a reading range up to 2.5 mm is demonstrated at 865 MHz. Anti-collision algorithm and memorized x–y device coordinates allow IC identification on the wafer under test to be achieved. Thanks to its cost-effectiveness, the proposed approach can be easily extended to general purpose IC contactless testing. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a power transfer system performing a dc–dc conversion with on-chip galvanic isolation. The converter is operated in the VHF band, which enables fully integration of all the required components in silicon technology. It consists of only two silicon dice, i.e., a power oscillator with an on-chip isolation transformer and a full-bridge rectifier, which are fabricated in 0.35–µm BCD and 0.13–µm CMOS technology, respectively. A thick SiO2 layer was used, which guarantees galvanic isolation between the transformer windings. A co-design procedure for the system building blocks is proposed, which aims at optimizing the dc–dc converter performance in terms of power efficiency at a given power density. Thanks to the adopted approach, a maximum output power up to 980 mW is demonstrated with a power efficiency of 29.6%. This paper outperforms previously reported integrated inductive step-up converters in terms of power per silicon area (up to 105 mW/mm2), while providing on-chip galvanic isolation without any discrete devices or post-processing steps. [ABSTRACT FROM PUBLISHER]

The analysis and modeling of monolithic interstacked transformers for mm-wave applications is addressed. The performance advantages of the interstacked structure are demonstrated by using the most important figures of merit for integrated transformers and a physic-based scalable lumped model is proposed. The model components are calculated with closed-form expressions that make use of geometrical and technological parameters. The accuracy of the proposed model is demonstrated by comparison with electromagnetic data in a wide frequency range. Maximum errors are below 5, 7.5, and 2% for magnetic coupling factor, quality factor, and self-resonance frequency, respectively. High accuracy is also achieved in the modeling of S-parameters up to the self-resonance frequency. [ABSTRACT FROM AUTHOR]

A lumped scalable model of silicon integrated inductors for RF IC design is presented. It was validated up to 20 GHz using measured performance parameters of more than 70 single-ended and differentially driven spirals covering 0.2- to 8.3 nH inductance values. Excellent accuracy, full geometrical scalability, compactness and high capability for implementation in circuit simulators promote the proposed model as a reliable time-saving design tool. Two circuital example, i.e., 5-GHz down-converter and 10-GHz VCO, are also presented to demonstrate its use in practical cases. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [ABSTRACT FROM AUTHOR]

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than ±0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level. [ABSTRACT FROM AUTHOR]

Abstract This work presents a review of integrated transformers for galvanic isolation with particular focus on their modelling in power transfer systems. A comparison between transformer-coupled oscillator topologies is carried out, highlighting the main differences in the realization of the isolation transformers. Lumped geometrically scalable modelling of the most adopted isolation transformer topologies are presented and compared. Transformer models have been validated by means of electromagnetic simulations in a wide range of geometrical parameters, achieving absolute errors lower than 12% for inductance, Q -factor peak, self-resonance frequency, and magnetic coupling factor. Highlights • A review of integrated transformers for galvanically isolated dc-dc converters. • Scalable lumped models of three different transformer configurations are compared. • The results can be exploited within an iterative co-design procedure. [ABSTRACT FROM AUTHOR]