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Anisotropic etching of deep trench in bulk Si for isolating global buried collector in Si monolithic microwave integrated circuit has been successfully developed with SF/sub 6//C/sub 2/CIF/sub 3/ gas mixtures. Using photoresist as the etching mask, deposition of polymer thin film on the sidewalls of the trench occurred, hence inhibited lateral etching and made the process anisotropic. Under optimal process conditions, an etching anisotropy of 0.98 and an etching selectivity of silicon to photoresist higher than 28 were observed.

The self-planarization of deep trench with 2 micron thick field oxidation has been developed for Si monolithic microwave integrated circuit (Si MMIC). Trenches with geometry of 2 /spl mu/m wide by 6/spl mu/m deep can be filled and planarized simply by a local oxidation of silicon (LOCOS) without polysilicon re-filling or etching back, while maintained a collector-to-collector leakage of 5 /spl mu/a at 15 V.

Presents both electrical and optical simulations of Si guided-wave electro-optic modulators. The simulation starts with design of modulators using a 2D semiconductor process simulator. The electrical properties of the modulators are analyzed by a 2D device simulator. Thereafter, the simulated electrical parameters are converted into optical parameters by proper electro-optic coefficients. The optical simulations are performed with both finite-difference-time-domain (FDTD) and mode-propagation-by-Fourier-expansion (MPFE) methods. The advantages of combining and using these two algorithms together are better accuracy and capability of analyzing arbitrarily shaped and optically large structures. The technique is illustrated by simulation and analysis of a series of Si guided-wave electro-optic modulators. >

Silicon piezoresistive stress sensors are used to measure stress on a plastic-encapsulated silicon die. These sensors are conventionally fabricated onto the surface of silicon integrated circuit die as part of the normal processing procedure. Since they can also be used over a wide temperature range after calibration, thermally-induced stresses can be measured. A four-point bending (4PB) stress fixture was used in calibration experiments. The results between the four-point resistance measurement and two-point resistance measurement of the strain gauges were compared. The problem in the calibration process was discussed.

A sealed wedge-shaped silicon power triode has been fabricated by CMOS compatible technology. The fabricated field emitter has higher thermal and mechanical stability due to the Eiffel Tower shape. The sealed structure eliminates the needs for external vacuum pumping and improves the reliability and lifetime of the device. Anode currents were demonstrated at anode voltages less than 4 volts.

A series of optical and electrical measurements of a-SiC:H/c-Si heterojunctions prepared by a parallel-plate plasma-enhanced chemical vapor deposition system are reported. All the samples underwent various passivation processes. It is observed that in situ H/sub 2//Ar plasma prior cleaning and H/sub 2/ plasma annealing can reduce the dark current of the heterojunction by three orders of magnitude. Higher process pressure and lower power density also favour good interface properties. >