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We have measured the low-frequency 1/ f noise of Si0.55Ge0.45 p MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( \textitS {vd} ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device. [ABSTRACT FROM PUBLISHER]

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ( \rho c ) of (1.3 – 1.5) \times 10^-9 ~\Omega \cdot \text cm^2 on Si:P. This PCAI + TiSix technique utilizes light amorphization (low-energy implantation), thin Ti and TiSix film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSix-induced \rho c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced \rho c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low \rho c is strongly correlated with the formation of interfacial TiSix crystallites between amorphous TiSi alloy and Si. [ABSTRACT FROM PUBLISHER]

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height ( q\varphi b) MIS contact: Ti/TiO2/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO2/n-Si thermal stability study under different electron conduction mechanisms. We find that both q\varphi b and contact resistivity ( \rho c) of the Ti/TiO2/n-Si MIS contacts vary dramatically after mere 300 °C–500 °C 1-min rapid thermal treatments. The variations in q\varphi b and \rho c are related to the thermally driven TiO2 decomposition. This thermal stability study of Ti/TiO2/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed. [ABSTRACT FROM PUBLISHER]

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( L\mathrm{eff} ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

The goal of this paper is to study the analog performance parameters of tunnel field-effect transistors (TFETs) with different source compositions and process conditions. The experimental matrix included devices with either a 100% silicon or Si1–xGex source, so that the germanium amount at the source/channel interface could be correlated with the prevailing transport mechanism and its impact on transconductance (gm), output conductance ( g\mathrm {DS} ), and early voltage ( V\mathrm {EA} ) could be analyzed. The used process conditions were highlighted by comparing a reference split with no Si passivation to the cases with 12 and 18 Si monolayers to determine their influence on the interface trap density and eventual reduction of the traps in the gate oxide. All these process parameters enable to make conclusions on the intrinsic voltage gain ( AV ) and the low-frequency noise. Based on these results, the suitability of each type of TFET has been discussed, revealing that 100% Si may still be considered for analog applications depending on the bias conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices. [ABSTRACT FROM AUTHOR]