Search

Single crystal Silicon-Germanium multi-quantum well layers were epitaxially grown on silicon substrates. Very high quality films were achieved with high level of control utilizing recently developed MHAH epitaxial technique. MHAH growth technique facilitates the monolithic integration of photonic functionality such as modulators and photodetectors with low-cost silicon VLSI technology. Mesa structured p-i-n photodetectors were fabricated with low reverse leakage currents of ~10 mA/cm² and responsivity values exceeding 0.1 A/W. Moreover, the spectral responsivity of fabricated detectors can be tuned by applied voltage.

We report the room temperature electroluminescence (EL) at 1.6 microm of a Ge n+/p light emitting diode on a Si substrate. Unlike normal electrically pumped devices, this device shows a super linear luminescence enhancement at high current. By comparing different n type doping concentrations, we observe that a higher concentration is required to achieve better efficiency of the device. Thermal enhancement effects observed in temperature dependent EL spectra show the capability of this device to operate at room temperature or above. These detailed studies show that Ge can be a good candidate for a Si compatible light emitting device.

For the first time, a novel analytical model of contact resistance (${R}_{\text{contact}}$) in vertically stacked nanosheet FETs (NSHFETs) with a silicide/Si (100) contact for a sub-3-nm node is presented. Generally, ${R}_{\text{contact}}$ consists of the interface resistance (${R}_{\text{interface}}$) and spreading resistance (${R}_{\text{spread}}$). Herein, a new model of ${R}_{\text{interface}}$ of silicide/Si (100) contact, which simultaneously considers the source/drain (S/D) doping concentration (${N}_{\text{si}}$), Schottky barrier height (SBH), and SBH lowering, is demonstrated simultaneously. In addition, a new model of ${R}_{\text{spread}}$ that divides S/D into multiple resistance components for vertically stacked NSHFETs is suggested. In vertically stacked NSHFET with 3-nm node, for TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, ${R}_{\text{spread}}$ shows more than ~50.0% higher values compared to ${R}_{\text{interface}}$. On the other hand, 3-nm node FinFET with TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, ${R}_{\text{spread}}$ shows more than ~53.7% lower values compared to ${R}_{\text{contact}}$. The results show that ${R}_{\text{spread}}$ becomes dominant in ${R}_{\text{contact}}$ compared to ${R}_{\text{interface}}$ when using NSHFETs, in contrast to the conventional FinFETs in which ${R}_{\text{interface}}$ is dominant in ${R}_{\text{contact}}$. The high ${R}_{\text{spread}}$ of the NSHFET is mainly caused by the low nanosheet thickness and vertical pitch between the nanosheets. This study provides critical insights into the design of the source/drain of NSHFET for sub-3-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. When the MIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal–semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node. [ABSTRACT FROM AUTHOR]

A new method of forming an ohmic contact without an increase in parasitic resistance is proposed in the Ti/GeO2/Ge substrate. Fermi-level depinning in Ti/GeO2/n–Ge contacts is possible with the formation of an interfacial TiOx layer in the contacts via an interfacial reaction. Unlike the intentional deposition of a metal oxide on a Ge substrate, this method provides easy process integration to lessen Fermi-level pinning in n-type Ge substrates. [ABSTRACT FROM PUBLISHER]

Here, we theoretically and experimentally investigate the impact of a high- \kappa layer inserted between graphene and p-Si in a graphene/Si junction. We have achieved 86-fold and 222-fold reductions in a specific contact resistivity ( \rho _{c} ) by inserting 1-nm-thick Al2O3 and 2-nm-thick TiO2 in the graphene–semiconductor junction, respectively, corresponding to lowering the effective barrier height by 0.24 and 0.12 eV. Furthermore, we propose a graphene-induced gap state model that simultaneously considers the graphene’s modulation by a gate bias and the effect of the high- \kappa $ insertion. [ABSTRACT FROM PUBLISHER]

Selective-area germanium (Ge) layer on silicon (Si) is desired to realize the advanced Ge devices integrated with Si very-large-scale-integration (VLSI) components. We demonstrate the area-dependent high-quality Ge growth on Si substrate through \SiO2 windows. The combination of area-dependent growth and multistep deposition/hydrogen annealing cycles has effectively reduced the surface roughness and the threading dislocation density. Low root-mean-square surface roughness of 0.6 nm is confirmed by atomic-force-microscope analysis. Low defect density in the area-dependent grown Ge layer is measured to be as low as \1 \times \10^7 \ \cm^-2 by plan-view transmission-electron-miscroscope analysis. In addition, the excellent metal–semiconductor–metal photodiode characteristics are shown on the grown Ge layer to open up a possibility to merge Ge optoelectronics with Si VLSI. [ABSTRACT FROM AUTHOR]

We demonstrate novel Ge n-MOSFETs with raised source/drain (S/D) fabricated on high-quality single-crystal Ge selectively grown heteroepitaxially on Si. For the raised S/D, an implant-free in situ doping technique has been employed for low-resistance, abrupt, and shallow \n^+/\p junctions. The novel n-MOSFETs show an excellent on/off ratio (\4 \times \10^3) with very high on current (3.23 \mu\A/\mu\m) and relatively high electron mobility on (100) Ge among the Ge n-MOSFETs. These results show promise toward monolithic integration of Ge MOSFETs with a Si VLSI platform. [ABSTRACT FROM AUTHOR]