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This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V. [ABSTRACT FROM AUTHOR]

A novel diagonal square array junction barrier Schottky (JBS) diode is created to enhance the forward current and reverse breakdown voltage by increasing the Schottky contact area and shortening the diagonal spacing between two adjacent p+ islands in the active area of a JBS diode. The shape of the p+ islands is square and the positional arrangement of the p+ islands is a diagonal array. Half of the upper and lower p+ islands with smaller areas are connected with the innermost p+ guard ring to create more Schottky contact area and laterally extend the electric field to the edge termination. Results show that the forward current density and reverse breakdown voltage for the diagonal square array JBS diode are 4.2% and 10.7% higher than those for the conventional square array JBS diode, respectively. As the spacing increases, the breakdown voltage for the diagonal square array JBS diode and the conventional square array JBS diode decrease by 3.5% and 7.3%, respectively, indicating that the diagonal square array JBS has more uniform depletion regions and electric field to retain the breakdown voltage. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30- \mu m thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11\,\times \,10^{\mathrm {12}} /cm ^{2} to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19\times 10^\mathrm 12 /cm ^2 to the positive surface charges, both superior to other JTE structures investigated in this paper. [ABSTRACT FROM AUTHOR]

Abstract: Thermal and pulsed excimer laser treatments have been applied for the post-implant anneals of Al- and N-implanted 3C-SiC samples to recover crystal damage caused by the ion implantation. FTIR reflectivity spectra show that the thermal anneal carried out at 1350°C for 30min has the better damage recovery in a range of the reststrahlen bands of both Al- and N-implanted samples. However, shoulders in the XRD spectra caused by the implantation indicate that a thermal anneal cannot completely recover the damage throughout an entire sample. For the Al-implanted samples, laser pulses with various energy densities can move shoulders to higher 2θ angles and then merge shoulders with the major peaks at the total energy density of 583.7J/cm2. 150 shots of laser pulses at the energy density of 256mJ/cm2 and combining with other energy densities can be used to recover damage in a range of the reststrahlen band which is induced by laser irradiation. Furthermore, the damage caused by the implantation in N-implanted samples is not close to the major peak in the XRD spectra, which can be improved by the laser pulses as well, but not moved to higher 2θ angles. However, the applied energy densities create extra damage in a range of the reststrahlen band. [Copyright &y& Elsevier]

The correlation between barrier inhomogeneities of 4H-SiC Schottky barrier diodes (SBDs) and surface defects and traps for SBDs fabricated with and without chemical–mechanical polishing (CMP) is investigated. 60% of the barrier inhomogeneities of SBDs with invisible surface defects are eliminated when CMP is applied in the refabrication. About 40% of SBDs with carrots inside the active areas exhibit double barriers without using CMP. This excludes that carrots are a cause of barrier inhomogeneities. However, none of the barrier inhomogeneities of the SBDs with carrots can be eliminated by using CMP. Most barrier inhomogeneities of SBDs with various surface defects inside the active areas can be improved by CMP. The difference between the high and low barrier heights of an SBD with CMP was reduced to about 0.02–0.06 eV. Therefore, the leakage current induced by barrier inhomogeneities is also reduced by CMP. Moreover, SBDs with a resistive termination extension (RTE) have a higher barrier height than SBDs without RTE, and there is no direct evidence to show that the inclusion of RTE can induce barrier inhomogeneities. [ABSTRACT FROM AUTHOR]

Design and fabrication of 4H–SiC lateral high-voltage devices on semi-insulating substrates based on the charge compensation principle have been investigated in this work. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, the breakdown voltage (BV) of a single-zone reduced-surface-field (RESURF) device with a 100- \mu\m drift region can be improved from 3360 to 5880 V. The BV can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in BV by 10% charge imbalance variation is also improved from 49% for a single-zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. A 4H–SiC JFET with a two-zone RESURF region was fabricated to demonstrate the advantages of lateral devices based on these concepts. The fabricated lateral 4H–SiC JFET has a BV of 4200 V and a specific on -resistance of 454 \m\Omega\cdot \cm^2. The figure of merit is as high as 38.8 \MW/cm^2. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, nitrogen-doped 4H-Silicon carbide (SiC) epilayers are grown on 4° off-axis C-face 4H-SiC substrates by horizontal hot-wall chemical vapor deposition. Surface morphology of the epilayers shows a strong dependence on N2 flow, C/Si ratio and growth temperature. Surface defect densities are higher for samples grown under high C/Si ratio and high N2 flow condition. Lightly doped epilayers with low defect densities have been achieved by growing under optimized conditions. Macrostep bunching is observed on epilayers grown under high N2 flow condition. The degree of step bunching manifests a dependence on N2 flow. Possible impurity-induced step-bunching mechanism is discussed to explain the results. Lightly doped C-face 4H-SiC epilayers exhibit a site-competition effect, while heavily doped epilayers do not. Schottky barrier diodes fabricated on C-face 4H-SiC epilayers are shown to be comparable to or outperform those on Si-face epilayers. [Copyright &y& Elsevier]

This research proposes a novel 4H-SiC power device structure—different concentration floating superjunction MOSFET (DC-FSJ MOSFET). Through simulation via Synopsys Technology Computer Aided Design (TCAD) software, compared with the structural and static characteristics of the traditional vertical MOSFET, DC-FSJ MOSFET has a higher breakdown voltage (BV) and lower forward specific on-resistance (Ron,sp). The DC-FSJ MOSFET is formed by multiple epitaxial technology to create a floating P-type structure in the epitaxial layer. Then, a current spreading layer (CSL) is added to reduce the Ron,sp. The floating P-type structure depth, epitaxial layer concentration and thickness are optimized in this research. This structure can not only achieve a breakdown voltage over 3300 V, but also reduce Ron,sp. Under the same conditions, the Baliga Figure of Merit (BFOM) of DC-FSJ MOSFET increases by 27% compared with the traditional vertical MOSFET. Ron,sp is 25% less than that of the traditional vertical MOSFET. [ABSTRACT FROM AUTHOR]