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The snubber circuit is a cost-effective solution to reduce the severe turn-off overvoltage and oscillation caused by the fast switching characteristics of SiC MOSFET. However, the turn-on switching losses will significantly increase as the snubber decouples the power loop parasitic inductance during the switching process. In this article, the effect of the power loop parasitic inductance on the switch performance of SiC MOSFETs and the quasi-zero voltage switching (QZVS) turn-on condition are studied. On this basis, an SiC MOSFET overvoltage and oscillation suppression circuit (OVSC) with not only the switching losses optimization feature but also the clamping energy feedback characteristic is proposed. The overvoltage and oscillation can be effectively suppressed by clamping capacitors, and those capacitors do not participate in the switching process until the overvoltage occurs, which is of benefit to the switching losses reduction compared with the other normal snubber circuits. Besides, the turn-off overvoltage and oscillation energy stored in the clamping capacitors can be feedback to dc and load side through a passive branch composed of an energy feedback inductor and a diode. The experimental studies and comprehensive comparison studies are carried out to verify the validity of the proposed OVSC. The experimental results show that OVSC has excellent overvoltage and oscillation suppression performance and can significantly reduce the switching losses. [ABSTRACT FROM AUTHOR]

Wide bandgap semiconductors show superior material properties enabling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) present good features on its switching speed and withstand voltage. However, the high voltage and fast switching characteristics of SiC MOSFETs also put forward new requirements for voltage measurement, that is, high bandwidth under high voltage conditions. This article proposes a new voltage divider structure and a proactive parameter design compensation network to build high voltage and high bandwidth voltage sensing circuit. This structure utilizes the characteristics that the same resistor has the same parasitic capacitance to meet the high frequency constraints of the voltage sensing circuit. The influence of parasitic parameters and load parameters on circuit performance is analyzed in detail, which provides a basis for the compensation network design. By combining the proposed voltage sensing circuit with an appropriate proactive parameter design load effect compensation network (PDCN), the withstand voltage rating of the low-voltage and high-bandwidth voltage probes can be extended to required levels. Different from other existing methods, PDCN can actively design the compensation circuit parameters and provide the optimal parameters of the compensation circuit. This lead to a smaller input capacitance than the state of the art commercial voltage probes, which will help to obtain better performance when measuring high-speed switching voltage. The performance of the voltage measurement is experimentally verified and compared by SiC-based double pulse test (DPT) circuits. [ABSTRACT FROM AUTHOR]

Current sense resistor (CSR) is widely used due to cost and integration considerations in industrial applications. However, when CSRs are used to sense transient currents caused by power device switching, especially fast-switching silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets) with high di/dt, even a tiny parasitic inductance in CSRs bring a significant impact on its sensing performance. This article proposes a low-cost well-performance and easy-to-design current sensing circuit that uses the CSRs and an LR compensation network (LRCN) to compensate for the effect of parasitic inductance on transient current sensing. In order to support the parameter selection of the LR network, the effects of parameters such as parasitic capacitance, parasitic inductance, and loads on the performance of the proposed current sensing circuit are analyzed in detail. Meanwhile, a parasitic inductance measurement method that only needs passive probes is proposed to measure and calculate the parasitic inductance of CSRs. This circuit can not only sense the transient current on the printed circuit board level but also observe the transient current on the oscilloscope through a coaxial cable connection. Finally, experimental studies under an inductive load double pulse test setup with SiC mosfets are carried out to verify the validity and feasibility of the proposed transient current sensing circuit. Only a high self-resonant frequency inductor and a surface mounted device resistor are needed to form the LR network to fully compensate the effect of parasitic inductance on CSRs. [ABSTRACT FROM AUTHOR]

Compared with silicon insulated-gate bipolar transistor, silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (mosfet) presents good features that it clearly shows on its switching and thermal performance. However, the fast switching speed of SiC mosfet makes it much more difficult for solving the dynamic voltage imbalance problem caused by the parameter fluctuations of the SiC mosfets and drive circuits when they are connected in series. This article proposes an effective gate drive circuit and its dynamic voltage balancing control method to tackle this issue. The proposed method not only balances the dynamic voltage during high-speed switching but also adapts to the variation of the dc-bus voltage by utilization of overdrive control method (ODCM). Furthermore, to widen the control range of the ODCM, a switched-capacitor compensation method by switching and combining different drive capacitors into different values is proposed. The operation principles and the parameter design method are discussed in detail. The performance of the proposed series-connected SiC mosfets gate drive circuit and its dynamic voltage balancing control method is validated by experimental results. The dynamic voltage can be well balanced within the design range. [ABSTRACT FROM AUTHOR]

Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfets to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on-state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has a more serious voltage overshoot than the silicon insulated gate bipolar transistor (IGBT) due to the fundamental differences of the devices’ parasitic parameters. In this paper, a novel low-inductance packaging structure for a wire-bond-based multichip phase-leg SiC MOSFET module to suppress the voltage overshoot is proposed. This packaging structure is based on the adjacent decoupling concept achieved by several decoupling capacitors to reduce the size of the commutation loop. The improvement in the packaging parasitics has been verified through an Ansys Q3D extractor. Furthermore, the influence of adjacent decoupling capacitors is analyzed in detail by frequency-domain analysis and verified with LTspice simulation analysis. Thereafter, the selection and thermal reliability of adjacent decoupling capacitors are expounded. The experimental results demonstrate the effectiveness and superiority of the proposed packaging structure. [ABSTRACT FROM PUBLISHER]

This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET). Two series-connected SiC MOSFETs with the proposed circuit only require a single standard gate driver to achieve the gate control and voltage balancing during both steady-state and switching transition. Moreover, the proposed circuit is only composed of ten passive components. Therefore, the proposed circuit provides a low-cost and highly reliable method to increase the blocking voltage of the SiC MOSFET. The operation principles of the proposed circuit are theoretically analyzed. In addition, the high-blocking-voltage device is not only required in switching-mode power supply (SMPS) but also in dc-breaker applications. The proposed circuit is then modified to make it suitable to the dc-breaker applications. The simulation and experimental results validate the effectiveness and superiority of the proposed circuit in both SMPS and dc-breaker applications. [ABSTRACT FROM PUBLISHER]