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Considering potential applications related to superconductivity and aerospace (typically less than 100 K), in this article, the temperature dependence of silicon carbide (SiC) power diodes is systematically characterized and analyzed over a wide temperature range of 90–478 K, especially focusing on cryogenic temperature. First, the static performance degradation mechanism of SiC diodes is established in an ultrawide temperature range, including forward/reverse I-V characteristics and junction capacitance (Cj) characteristics. Second, the reverse recovery characteristics are achieved, including peak reverse recovery current (Irm), reverse recovery charge (Qrr), and switching energy (Esw), clarifying a clearer internal relationship between reverse recovery and junction temperature. Meanwhile, the aforementioned critical parameters are further analyzed on an electrical scale with normal atmosphere temperature, including switching speed range of 62.3–2054.8 A/μs, load current range of 6–30 A, and dc voltage range of 400–1000 V. Third, based on newly proposed power loss analysis method, the continuous operation performance of SiC diodes is quantified and analyzed in actual cryogenic converters. The excellent temperature dependence indicates that SiC diodes have great superiority for extreme applications. Importantly, SiC mosfet's body diode shows the great potential to operate as a freewheeling diode in the compact converter, especially at cryogenic temperature. [ABSTRACT FROM AUTHOR]

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance (${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$) and threshold voltage (${V}_{\text {th}}$) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times (${T}_{r}$ and ${T}_{f}$) and the corresponding energy loss (${E}_{r}$ and ${E}_{f}$) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm ^2 /Vs, and the specific ON-resistance and the BV were 1.64 \textm\Omega \cdot cm^2 ( V\mathrm {GS}= 15 V, V\mathrm {DS}= 1 V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation. [ABSTRACT FROM AUTHOR]

In this letter, an improved 4H–SiC step trench-gate power metal–oxide–semiconductor field-effect transistor (MOSFET) with a p-n junction in the trench is proposed. The step trench significantly reduces the ON-resistance of the device. And the p-n junction in the trench reduces the gate charge. Compared with the conventional p+ shielding trench MOSFET structure, simulation results show that the specific ON-resistance and gate charge of the proposed device are improved by 26.4% and 34.7%, respectively. A 43.4% improvement in the figure of merit (including the breakdown voltage and ON-resistance) is also observed. [ABSTRACT FROM PUBLISHER]

A 10 kV 4H–SiC epitaxial PiN diode is fabricated and the measured static on-state current voltage characteristics are used to tune the physical models and parameters included in TCAD device simulations. From the measurements it is found that the on-state voltage drop decreases more than 0.5 V at a current density of 100 A/cm2, as the temperature is raised from room temperature to 300 °C. The steep slope of the IV-curve is, furthermore, maintained at elevated temperatures in contrast to most silicon PiN structures, where the decrease in mobility at higher temperatures typically decreases the IV slope, resulting in an increased voltage drop. Physical device simulations, involving common models for bandgap, incomplete ionization, charge carrier lifetime and mobility, are systematically compared and optimized to obtain the best fit with measured data. The negative temperature dependence can be simulated with good precision although the fitting is very sensitive to the choice of mobility models and, in particular, the acceptor ionization energy. [ABSTRACT FROM AUTHOR]