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Given the high complexity of the conventional three-level space-vector pulsewidth modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced. [ABSTRACT FROM AUTHOR]

The adoption of fast-switching silicon carbide (SiC) devices enables power converters to operate at high switching frequencies (e.g., 100 kHz). However, as a limiting factor at high switching frequencies, the dead-time in the conventional pulsewidth modulation (PWM) can cause significant voltage losses, bring serious low-frequency voltage/current harmonics, and reduce the linear modulation region with lower dc-link voltage utilization. Using the dead-time compensation can effectively eliminate the dead-time effect but further reduce the linear modulation region. The dead-time elimination PWM essentially has no dead-time effect. But due to the abandon of drive pulses for generating synchronous rectification, it has a lower converter efficiency, as well as current jumps at zero-crossings. In this article, to overcome the drawbacks of the conventional PWM and the dead-time elimination PWM, a double-modulation-wave PWM for dead-time-effect elimination and synchronous rectification is therefore proposed, where extra drive pulses for generating synchronous rectification are added based on the dead-time elimination PWM. The added drive pulses can also help with mitigating current jumps at zero-crossings. At last, the proposed PWM is experimentally validated and compared with the conventional PWM and the dead-time elimination PWM at 100 kHz on a three-phase converter with SiC mosfets and SiC Schottky diodes, showing the merits of low voltage losses, low output harmonics, high dc-link voltage utilization, large linear modulation region, and high efficiency. [ABSTRACT FROM AUTHOR]

The adoption of silicon carbide (SiC) MOSFETs and SiC Schottky diodes in power converters promises a further improvement of the attainable power density and system efficiency, while it is restricted by several issues caused by the ultrafast switching, such as phase-leg shoot-through (“crosstalk” effect), high turn-on losses, electromagnetic interference (EMI), etc. This paper presents a split output converter, which can overcome the limitations of the standard two-level voltage source converters when employing the fast-switching SiC devices. A mathematical model of the split output converter has been proposed to reveal how the split inductors can mitigate the crosstalk effect caused by the high switching speed. The improved switching performance (e.g., lower turn-on losses) and EMI benefit have been demonstrated experimentally. The current freewheeling problem, the current pulses and voltage spikes of the split inductors, and the disappeared synchronous rectification are explained in detail both experimentally and analytically. The results show that the split output converter can have lower power device losses compared with the standard two-level converter at high switching frequencies. However, the extra losses in the split inductors may impair the efficiency of the split output converter, which is verified by experiments in the continuous operating mode. A 95.91% efficiency has been achieved by the split output converter at the switching frequency of 100 kHz with suppressed crosstalk, lower turn-on losses, and reduced EMI. [ABSTRACT FROM AUTHOR]