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The exponential demand for bandwidth in data centers is on high alert with the increase in data traffic. In this scenario, the design of optical modulators is crucial for the continuous evolution of communication systems. For data center interconnect (DCI) applications, this mean that modulators should offer high bandwidth and low optical loss. In addition, devices must operate with low power consumption and be compatible with complementary metal–oxide–semiconductor (CMOS) processes for low-cost and large-scale manufacturing. These facts show the importance of advancement in Silicon (Si) modulators solutions, since they have the potential to fulfill all these requirements. However, designing a device that meets all these requirements at the same time is still challenging, because there are several trade-offs problems involved for which different Silicon modulators types are not yet able to solve. In this context, this paper reviews the challenges in Silicon photonics (SiPh) modulators for data center interconnect applications.

In this work, a polarization splitter-rotator in the SOI platform is demonstrated, based on the evanescent coupling to a polysilicon waveguide. The device is compact (< 30µm), low loss (< −1.5dB) and simple to fabricate.

We propose and demonstrate a polarization splitter and rotator (PSR) operating in the range of 1530–1590 nm, built on the SOI platform and based on a new bow tie converter TM0-to-TE1. Comparing with other compact (

We demonstrate a broadband and polarization insensitive 3 dB power splitter compatible with CMOS process. The simulation results show low insertion loss in the wavelength range from 1460 to 1640 nm for both TE and TM polarization. The fabricated device has a maximum insertion loss of 0.5 dB and 0.07 dB for TE and TM polarization, respectively, from 1520 to 1580 nm wavelength.

This paper presents a capacitive modulator design and modeling using poly-si and silicon technologies. We propose a methodology involving the entire modulator design process, from the optical design, charge distribution calculation and small-signal RF analysis. Thus, in the case of silicon photonics modulators, the paper proposes means to optimize the trade-offs among several figures of merit. It is shown that high bandwidth operation (>30 GHz) can be achieved by sacrificing a little the modulation efficiency. info:eu-repo/semantics/publishedVersion

We propose a fiber-chip edge coupler based on a subwavelength grating in silicon-on-insulator (SOI) platform for coupling to cleaved and high numerical aperture (HNA) optical fibers (mode field diameter of 6.3 μm). Its robustness to fabrication errors and high tolerance to fiber misalignment (±1.5 μm for a 1 dB of excess loss) make it suitable for high-volume production, being a potential candidate for data center applications. Simulation results show a 1 dB bandwidth higher than 200 nm, a polarization dependent loss lower than 0.5 dB, and minimum coupling losses of 1.47 and 1.39 dB for TE and TM modes, respectively, considering a 204 μm-long mode converter.

This chapter describes the development of passive and active components for silicon photonic integrated circuits that were performed in the CPqD. Specifically, the devices studied are polarization splitter and rotator (PSR), optical \(90^{\circ }\) hybrid, modulator, and laser. Each one is explained showing the principle of operation, modeling, and results obtained. These designed devices are compatible with standard manufacturing processes enabling monolithic integration with other devices. In addition, they can be used as building blocks for coherent transceivers and receivers in silicon photonics.

In this work, we present a design for a high-bandwidth (> 40 GHz) O-band Silicon Mach-Zehnder modulator using a lateral junction and compare it with an interleaved junction in terms of efficiency, loss and bandwidth.

We present the concept and design of a hybrid integrated widely tunable III-V-on-silicon ring laser with 80 nm tuning range by means of theoretical investigation. Laser spontaneous emission is provided by two gain chips, one for the C band and the other for the L band. Gain chip sections are duplexed into the silicon photonic passive cavity using a lattice filter. Wavelength tunability is proposed using the Vernier effect between two ring resonators incorporated in the silicon photonic cavity. We present numerical results of modeled laser cavity using a time-domain circuit simulator optimizing the choice of the output mirror reflectivity. The simulated performance shows a waveguide output power up to 65 mW and a high SMSR (> 45 dB) over the entire wavelength range. Linewidth calculations show feasibility for high-order modulation formats.

Emerging short-reach data center interconnect (typically in the range of tens of km) is a scenario wherein the capacity has to be maximized over point-to-point optical links without intermediate optical amplification, i.e. unrepeated links. For this application, cost and compactness of the optical transceiver form factor to fit the faceplate density requirement are essential to keep up with the bandwidth demand inside hyper-scale data centers. For the optical module to fit in the current dimensions of client routers without compromising the performance, both the electronics and the optics have to be efficiently designed. As far as the opto-electronic is concerned, photonic integrated circuits (PIC) have been discussed in the community so that all the photonic functionalities are performed accordingly with the physical dimensions, power budget and performance specifications. This paper addresses the basic building blocks of silicon photonics coherent optical transceivers, from the design to experimental validation. In addition to the silicon optical modulator, basic components such as polarization splitter-rotators (PSRs) and optical filters will be addressed.

Silicon photonics has been widely researched as a potential technology for the next generation of optical devices due to its high integration capabilities. After presenting the first Brazilian high speed integrated 100G-DPQPSK transmitter, this paper brings the design and characterization of a compact integrated silicon coherent receiver, with a footprint of are 4.5 mm x 1 mm. The characterization was performed with 112 Gb/s DP-QPSK modulation resulting in an estimated BER of 5.46 x10 -7 .