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Using computer-aided design three-dimensional (3D) simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer (LET) threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability. [ABSTRACT FROM AUTHOR]

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient (SET) production in 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect (bipolar effect) in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the substrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P+-well layer and can be removed by a buried SO2 layer. [ABSTRACT FROM AUTHOR]

A comparison of the temperature dependence of the P-hit single event transient (SET) in a two-transistor (2T) inverter with that in a three-transistor (3T) inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure (or similar layout structures) will be a better solution for spaceborne integrated circuit design for extreme environments. [ABSTRACT FROM AUTHOR]

FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p-FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel (fin) conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient (SET) pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology. [ABSTRACT FROM AUTHOR]