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The adoption of RISC-V processors bloomed in recent years, mainly due to its open standard and free instruction set architecture. However, much remains to help software engineers deliver high-reliability and bug-free applications and systems based on RISC-V IP designs. This work proposes an early soft error reliability assessment of a RISC-V processor, extending the previously proposed SOFIA fault injection framework. Results from 850k fault injections show that choosing the compiler flag -O2 to optimize performance causes 96% more Hang failures than -O0. Software engineers must evaluate compilation parameters on a case-by-case basis to find the best balance between performance and reliability. This work helps software engineers develop fault-tolerant RISC-V-based systems and applications more efficiently. [ABSTRACT FROM AUTHOR]

Driven by the success of machine learning algorithms for recognizing and identifying objects, there are significant efforts to exploit convolutional neural networks (CNNs) in edge devices. The growing adoption of CNNs in safety-critical embedded systems (e.g., autonomous vehicles) increases the demand for safe and reliable models. In this sense, this brief investigates the soft error reliability of two CNN inference models considering single event upsets (SEUs) occurring in register files, RAM, and Flash memory sections. The results show that the incidence of SEUs in flash memory sections tend to lead to more critical faults than those resulting from the occurrence of bit-flips in RAM sections and register files. [ABSTRACT FROM AUTHOR]

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety–critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors at the initial design cycle. This paper presents SOFIA, a framework that integrates: (i) a set of fault injection techniques that enable bespoke inspections, (ii) machine learning methods to correlate soft error results and system architecture parameters, and (iii) mitigation techniques, including: full and partial triple modular redundancy (TMR) as well as a register allocation technique (RAT), which allocates the critical code (e.g., application's function, machine learning layer) to a pool of specific processor registers. The proposed framework and novel variations of the RAT are validated through more than 1739k fault injections considering a real Linux kernel, benchmarks from different domains and a multi-core Arm processor. [ABSTRACT FROM AUTHOR]