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We investigate electron and hole lateral migration in Vt retention loss in a multilevel charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In Vt retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and Vt traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that Vt retention loss in a program state exhibits a turnaround characteristic as program Vt level increases. Vt loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and Vt loss is dominated by electron vertical loss and lateral migration. [ABSTRACT FROM AUTHOR]

We investigated electric field-induced trapped electron lateral migration in a SONOS flash cell. The threshold voltage shift ( \Delta \textVt ) and gate-induced drain leakage (GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used to monitor trapped charge lateral migration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel–Poole emission were compared. [ABSTRACT FROM PUBLISHER]

A Vt retention distribution tail in a multitime-program (MTP) silicon–oxide–nitride–oxide–silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced \Delta Vt in nor-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-loss-induced \Delta Vt exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program Vt level in an MLC SONOS. In addition, we measure a Vt retention distribution in a 512-Mb MTP SONOS memory and observe a significant Vt retention tail. A numerical Vt retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured Vt retention distribution in a 512-Mb SONOS well. The observed Vt tail is realized mainly due to the percolation effect. [ABSTRACT FROM PUBLISHER]

Geometric effects on program/erase speeds, endurance, and charge retention of polysilicon-oxide-nitride-oxide-silicon-type memories are investigated with various structures, including Flash cells, capacitors, and NAND array strings of different dimensions. NAND strings with common word-lines or/and bit-lines were employed to characterize the Lg and W effect on device performance, which builds up the capability to extrapolate the cell properties of various dimensions. For a charge trapping storage device, it suggests that the evaluation carried out on a large-area device always leads to a conclusion more optimistic than the cell inside array of a real product in all aspects. In addition, a numerical model is proposed to elucidate the observed phenomena from a statistical viewpoint. [ABSTRACT FROM AUTHOR]

A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a nor-type silicon–oxide–nitride–oxide–silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state Vt retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10–20 program/erase cycles. Nitride charge vertical loss is verified by this method. [ABSTRACT FROM PUBLISHER]