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Ultrahigh-speed magnetization switching mechanism is strongly pursued, as it can improve the write performance of the magnetic random access memory (MRAM) and further extend the application area of spintronics. Currently, a well-studied switching mechanism is the spin transfer torque (STT), whose speed, however, is limited by an intrinsic incubation delay. Recently, spin–orbit torque (SOT) was proposed to solve the speed bottleneck of the STT. In this paper, we evaluate the potential of two types of SOT-MRAMs, whose data can be ultrafast written based on the recently discovered field-free SOT mechanisms, respectively. A cross-layer analysis is presented involving device modeling, circuit-level optimization, and architecture-level evaluation. First, the principle of the magnetization switching is analyzed with the macrospin simulation. Then, the optimization strategies at the circuit level are generalized through the SPICE-type simulation. Finally, we build up the memory architecture with the SOT-MRAMs, STT-MRAM, and static RAM. Their read/write performances are evaluated with NVSim software. It is demonstrated that one of the studied SOT-MRAMs shows the promising prospect in the non-volatile memory, especially suitable for high-capacity cache. [ABSTRACT FROM AUTHOR]

Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations. [ABSTRACT FROM AUTHOR]

A novel multi-bit non-volatile flip-flop (NVFF) written by spin-Hall-assisted spin-transfer torque (STT) is proposed. This NVFF employs perpendicular-anisotropy MTJs and requires an STT current combined with a spin-Hall current to write the data. Thanks to the assistance of spin-Hall effect (SHE), the incubation delay required by the conventional STT switching can be eliminated to achieve fast operation. Our proposed NVFF uses multi-bit architecture and shows high-density and low-energy advantages over hybrid NV/volatile FFs in the application of the NV register file. Sim-ulation results show that the proposed spin-Hall-assisted NVFF saves ∼31% storage density and ∼32% energy dissipation compared with the conventional STT-NVFF. Moreover, the reliability of MTJ barrier is enhanced due to the reduction of the write voltage. (© 2015 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradigms have been proposed to address this problem by adding a small amount of processing units inside/near the memory. Unfortunately, although intensively studied, prior IMP/NMP platforms are practically unsuccessful because of the fabrication complexity and cost efficiency by integrating the processing units and memory on the same chip. Recently, emerging nonvolatile memories provide new possibility for efficiently implementing the IMP/NMP paradigm. In this paper, we propose a cost-efficient IMP/NMP solution in spin-transfer torque magnetic random access memory (STT–MRAM) without adding any processing units on the memory chip. The key idea behind the proposed IMP/NMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations. Such an IMP/NMP platform enables rather fast logic operations as the logic results can be obtained immediately through just a memory-like readout operation. Memory read and logics not, and/nand, and or/nor operations can be achieved and dynamically configured within the same STT–MRAM chip. Functionality and performance are evaluated with hybrid simulations under the 40 nm technology node. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Highlights: [•] We analyse and model the reliability issue in STT-MRAM. [•] We present a low-cost OLSC circuit to improve STT-MRAM reliability. [•] Built-in-form implementation using STT-MRAM-based logic acts as an inner code. [•] Its simple codec provides very low area and high speed. [•] Modular codec structure enables adaptive error correction capability. [Copyright &y& Elsevier]

Magnetic anisotropy modulation is an effective method to simultaneously reduce the switching current and extend the data retention of magnetic tunnel junction (MTJ), which is promising to be used in the next-generation spin transfer torque (STT) magnetic random-access memory. However, to meet the requirements of high storage life and harsh environments, the improved perpendicular magnetic anisotropy of MTJ makes the conventional modulation methods suffer from high breakdown risk owing to the relatively low efficiency. In this paper, a method of phase-change controlled magnetic anisotropy (PCMA) is introduced to a physical model of VO2/CoFeB/MgO/CoFeB perpendicular MTJ with superior modulation capability proved by systematical simulation. The time sequence of phase change pulse and STT pulse is studied, proving that there exists a specific interval to achieve both rapid and low-power switching. With the joint effect of PCMA and STT, low-energy (68.2 fJ), low-error-rate (0.08), and fast (2 ns) write operation can be achieved in the MTJ accompanied by a high thermal stability factor (78). The results demonstrate that the PCMA-STT switching strategy is most suitable for MTJ with large perpendicular magnetic anisotropy, paving a promising way to replace NOR flash memories. [ABSTRACT FROM AUTHOR]

With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. Spin transfer torque magnetic memory (STT-MRAM) is proposed as a promising solution for the low power cache design due to its high integration density and ultralow leakage power. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM, and observe that the temperature can affect the write delay and energy significantly. Then, we explore the nonuniform cache access (NUCA) design of the chip-multiprocessors with STT-MRAM-based last level cache (LLC). A thermal aware data migration policy, called “Thermosiphon,” which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions dynamically based on the thermal distribution monitored by thermal sensors available on-chip, and adaptively migrates write intensive data among different thermal regions considering the thermal gradient. Compared to the conventional NUCA design, our proposed design can save 41.2% write energy at most and 13.01% on average with negligible hardware overhead. [ABSTRACT FROM AUTHOR]