Search

A two channel time-interleaved 14-bit 500MS/s charge domain pipelined ADC with mix-signal for-ground mismatch calibration method based on binary search is proposed. The offset and gain error mismatch between the two channels are calibrated in the mix-signal for-ground calibration. The 14-bit 500MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18$\mu$m CMOS process. Test results show the 14-bit 500MS/s ADC achieves the signal-to-noise ratio of 69.8 dBFS and the spurious free dynamic range of 82.3dB, with 72.1MHz input at 500MS/s, while consumes the power consumption of 365mW.

A low power 10-bit 250 MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) is introduced. The ADC is implemented in MOS bucket-brigade devices (BBDs) based CD pipelined architecture. A replica controlled boosted charge transfer (BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18 μ m CMOS process. The ADC achieves the SFDR of 64.4 dB, the SNDR of 56.9 dBFS and the ENOB of 9.2 for a 9.9 MHz input; and the SFDR of 63.1 dB, the SNR of 55.2 dBFS, the SNDR of 54.5 dBFS and the ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is +0.5/-0.55 LSB and INL is +0.8/-0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.4 LSB and integral nonlinearity (INL) is +0.8/-0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.