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The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation. [ABSTRACT FROM PUBLISHER]

We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques. [ABSTRACT FROM PUBLISHER]