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For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design. [ABSTRACT FROM AUTHOR]

This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the $6\sigma $ yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, R_{\mathrm {SD}} as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts. [ABSTRACT FROM PUBLISHER]

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications. [ABSTRACT FROM AUTHOR]

This paper analyzes the impacts of read-assist and write-assist circuits on GeOI FinFET 6T SRAM cells considering intrinsic random variations, process corner, and temperature variation. The word-line under-drive (WLUD) read-assist is more efficient to improve the read static noise margin and read $V_{{\rm {MIN}}}$ of fast-N slow-P corner GeOI FinFET SRAM cells compared with the Silicon-On-Insulator (SOI) counterparts. GeOI FinFET SRAM cells with WLUD show less cell read access-time degradation compared with the SOI counterparts at both 25 °C and 125 °C. With transient voltage collapse (TVC) write-assist, the write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC write-assist pulsewidth constrained by the data retention failure is smaller in GeOI FinFET SRAMs at 25 °C and becomes comparable at 125 °C compared with the SOI FinFET SRAMs. [ABSTRACT FROM AUTHOR]

This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications. [ABSTRACT FROM PUBLISHER]

With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push–pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance. [ABSTRACT FROM AUTHOR]